mips,cpu: Get rid of the IsCondDelaySlot StaticInst flag.
This is set by MIPS in a few places, but not actually used by anything. Change-Id: Iaf3b29b2c14bb1de3ffd6a0035f12f238591cb60 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33736 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
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@@ -241,7 +241,6 @@ def format Branch(code, *opt_flags) {{
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code += 'R31 = NNPC;\n'
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elif x == 'Likely':
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not_taken_code = 'NNPC = NPC; NPC = PC;'
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inst_flags += ('IsCondDelaySlot', )
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else:
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inst_flags += (x, )
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@@ -280,7 +279,6 @@ def format DspBranch(code, *opt_flags) {{
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code += 'R32 = NNPC;'
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elif x == 'Likely':
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not_taken_code = 'NNPC = NPC, NPC = PC;'
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inst_flags += ('IsCondDelaySlot', )
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else:
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inst_flags += (x, )
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@@ -78,8 +78,6 @@ class StaticInstFlags(Enum):
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'IsCall', # Subroutine call.
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'IsReturn', # Subroutine return.
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'IsCondDelaySlot', # Conditional Delay-Slot Instruction
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'IsThreadSync', # Thread synchronization operation.
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'IsSerializing', # Serializes pipeline: won't execute until all
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@@ -541,7 +541,6 @@ class BaseDynInst : public ExecContext, public RefCounted
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bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
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bool isCondCtrl() const { return staticInst->isCondCtrl(); }
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bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
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bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
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bool isThreadSync() const { return staticInst->isThreadSync(); }
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bool isSerializing() const { return staticInst->isSerializing(); }
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bool
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@@ -179,7 +179,6 @@ class StaticInst : public RefCounted, public StaticInstFlags
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bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
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bool isCondCtrl() const { return flags[IsCondControl]; }
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bool isUncondCtrl() const { return flags[IsUncondControl]; }
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bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
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bool isThreadSync() const { return flags[IsThreadSync]; }
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bool isSerializing() const { return flags[IsSerializing] ||
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