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mem-ruby: Unique ranks for MOESI_CMP_dir in ports

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Setting different values for the rank parameter for all inputs ports.
If left unset, it defaults to 0. This may cause issues since the rank is
used as an index in the controller's list of stalled buffers.

Change-Id: Ie8ff660b7450df959292311040aebf802657efcf
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18411
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Tiago Muck
2019-02-19 12:48:06 -06:00
committed by Tiago Mück
parent cbf74a79e6
commit 575ac7a14a
4 changed files with 15 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
View File

@@ -278,7 +278,7 @@ machine(MachineType:L1Cache, "L1 cache protocol")
// ** IN_PORTS **
// Use Timer
in_port(useTimerTable_in, Addr, useTimerTable) {
in_port(useTimerTable_in, Addr, useTimerTable, rank=4) {
if (useTimerTable_in.isReady(clockEdge())) {
Addr readyAddress := useTimerTable.nextAddress();
trigger(Event:Use_Timeout, readyAddress, getCacheEntry(readyAddress),
@@ -287,7 +287,7 @@ machine(MachineType:L1Cache, "L1 cache protocol")
}
// Trigger Queue
in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=3) {
if (triggerQueue_in.isReady(clockEdge())) {
peek(triggerQueue_in, TriggerMsg) {
if (in_msg.Type == TriggerType:ALL_ACKS) {
@@ -301,7 +301,7 @@ machine(MachineType:L1Cache, "L1 cache protocol")
}
// Response Network
in_port(responseToL1Cache_in, ResponseMsg, responseToL1Cache) {
in_port(responseToL1Cache_in, ResponseMsg, responseToL1Cache, rank=2) {
if (responseToL1Cache_in.isReady(clockEdge())) {
peek(responseToL1Cache_in, ResponseMsg, block_on="addr") {
if (in_msg.Type == CoherenceResponseType:ACK) {
@@ -331,7 +331,7 @@ machine(MachineType:L1Cache, "L1 cache protocol")
// Request Network
in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
in_port(requestNetwork_in, RequestMsg, requestToL1Cache, rank=1) {
if (requestNetwork_in.isReady(clockEdge())) {
peek(requestNetwork_in, RequestMsg, block_on="addr") {
assert(in_msg.Destination.isElement(machineID));
@@ -362,7 +362,7 @@ machine(MachineType:L1Cache, "L1 cache protocol")
}
// Mandatory Queue betweens Node's CPU and it's L1 caches
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") {
in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, rank=0) {
if (mandatoryQueue_in.isReady(clockEdge())) {
peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {

8
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
View File

@@ -592,7 +592,7 @@ machine(MachineType:L2Cache, "Token protocol")
// ** IN_PORTS **
// Trigger Queue
in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=3) {
if (triggerQueue_in.isReady(clockEdge())) {
peek(triggerQueue_in, TriggerMsg) {
if (in_msg.Type == TriggerType:ALL_ACKS) {
@@ -606,7 +606,7 @@ machine(MachineType:L2Cache, "Token protocol")
}
// Response Network
in_port(responseNetwork_in, ResponseMsg, responseToL2Cache) {
in_port(responseNetwork_in, ResponseMsg, responseToL2Cache, rank=2) {
if (responseNetwork_in.isReady(clockEdge())) {
peek(responseNetwork_in, ResponseMsg) {
assert(in_msg.Destination.isElement(machineID));
@@ -650,7 +650,7 @@ machine(MachineType:L2Cache, "Token protocol")
// Request Network
in_port(requestNetwork_in, RequestMsg, GlobalRequestToL2Cache) {
in_port(requestNetwork_in, RequestMsg, GlobalRequestToL2Cache, rank=1) {
if (requestNetwork_in.isReady(clockEdge())) {
peek(requestNetwork_in, RequestMsg) {
if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_WRITE) {
@@ -677,7 +677,7 @@ machine(MachineType:L2Cache, "Token protocol")
}
}
in_port(L1requestNetwork_in, RequestMsg, L1RequestToL2Cache) {
in_port(L1requestNetwork_in, RequestMsg, L1RequestToL2Cache, rank=0) {
if (L1requestNetwork_in.isReady(clockEdge())) {
peek(L1requestNetwork_in, RequestMsg) {
assert(in_msg.Destination.isElement(machineID));

6
src/mem/protocol/MOESI_CMP_directory-dir.sm
View File

@@ -241,7 +241,7 @@ machine(MachineType:Directory, "Directory protocol")
// ** IN_PORTS **
in_port(unblockNetwork_in, ResponseMsg, responseToDir) {
in_port(unblockNetwork_in, ResponseMsg, responseToDir, rank=2) {
if (unblockNetwork_in.isReady(clockEdge())) {
peek(unblockNetwork_in, ResponseMsg) {
if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
@@ -268,7 +268,7 @@ machine(MachineType:Directory, "Directory protocol")
}
}
in_port(requestQueue_in, RequestMsg, requestToDir) {
in_port(requestQueue_in, RequestMsg, requestToDir, rank=1) {
if (requestQueue_in.isReady(clockEdge())) {
peek(requestQueue_in, RequestMsg) {
if (in_msg.Type == CoherenceRequestType:GETS) {
@@ -301,7 +301,7 @@ machine(MachineType:Directory, "Directory protocol")
}
// off-chip memory request/response is done
in_port(memQueue_in, MemoryMsg, responseFromMemory) {
in_port(memQueue_in, MemoryMsg, responseFromMemory, rank=0) {
if (memQueue_in.isReady(clockEdge())) {
peek(memQueue_in, MemoryMsg) {
if (in_msg.Type == MemoryRequestType:MEMORY_READ) {

6
src/mem/protocol/MOESI_CMP_directory-dma.sm
View File

@@ -118,7 +118,7 @@ machine(MachineType:DMA, "DMA Controller")
out_port(respToDirectory_out, ResponseMsg, respToDir, desc="...");
out_port(triggerQueue_out, TriggerMsg, triggerQueue, desc="...");
in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, rank=2) {
if (dmaResponseQueue_in.isReady(clockEdge())) {
peek( dmaResponseQueue_in, ResponseMsg) {
if (in_msg.Type == CoherenceResponseType:DMA_ACK) {
@@ -139,7 +139,7 @@ machine(MachineType:DMA, "DMA Controller")
}
// Trigger Queue
in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=1) {
if (triggerQueue_in.isReady(clockEdge())) {
peek(triggerQueue_in, TriggerMsg) {
if (in_msg.Type == TriggerType:ALL_ACKS) {
@@ -151,7 +151,7 @@ machine(MachineType:DMA, "DMA Controller")
}
}
in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, rank=0) {
if (dmaRequestQueue_in.isReady(clockEdge())) {
peek(dmaRequestQueue_in, SequencerMsg) {
if (in_msg.Type == SequencerRequestType:LD ) {