mem-ruby: Ensure MOESI_AMD_Base-dir has probe destinations
The directory has an assert that this is at least one destination for a probe when sending an invalidation or shared probe to coherence end points in the protocol (TCC, LLC). This is not necessarily request and for certain configurations there will be no probes required and none will be sent. One such configuration is the GPU protocol tester which would not require a probe to the CPU if it does not exist. To fix this we first collect the probe destinations. Then we check if any destinations exist. If so, we send the probe message. Otherwise we immediately enqueue a probe complete message to the trigger queue. This reorganization prevents messages with no destinations from being enqueued, meeting the criteria for the assertion. Change-Id: If016f457cb8c9e0277a910ac2c3f315c25b50ce8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55543 Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Maintainer: Matt Sinclair <mattdsinclair@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
@@ -646,202 +646,274 @@ machine(MachineType:Directory, "AMD Baseline protocol")
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action(icd_probeInvCoreDataForDMA, "icd", desc="Probe inv cores, return data for DMA") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) {
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out_msg.addr := address;
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out_msg.Type := ProbeRequestType:PrbInv;
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out_msg.ReturnData := true;
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out_msg.MessageSize := MessageSizeType:Control;
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NetDest probe_dests;
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// Add relevant machine types based on CPUonly, GPUonly and noTCCdir:
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// CPUonly && GPUonly -> Invalid
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// CPUonly && !GPUonly -> Add CorePairs
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// !CPUonly && GPUonly -> Add TCCs or TCC dirs
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// !CPUonly && !GPUonly -> Add CorePairs and TCCs or TCC dirs
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if (CPUonly) {
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assert(!GPUonly);
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probe_dests.broadcast(MachineType:CorePair);
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} else {
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// CPU + GPU system
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if (!GPUonly) {
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out_msg.Destination.broadcast(MachineType:CorePair);
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probe_dests.broadcast(MachineType:CorePair);
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}
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// Add relevant TCC node to list. This replaces all TCPs and SQCs
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if (CPUonly) {
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// CPU only has neither TCC nor TCC directory to add.
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} else if (noTCCdir) {
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
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// CPU + GPU or GPU only system
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if (noTCCdir) {
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probe_dests.add(mapAddressToRange(address, MachineType:TCC,
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TCC_select_low_bit,
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TCC_select_num_bits));
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} else {
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out_msg.Destination.add(mapAddressToRange(address,
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MachineType:TCCdir,
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TCC_select_low_bit, TCC_select_num_bits));
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probe_dests.add(mapAddressToRange(address, MachineType:TCCdir,
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TCC_select_low_bit,
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TCC_select_num_bits));
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}
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out_msg.Destination.remove(in_msg.Requestor);
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tbe.NumPendingAcks := out_msg.Destination.count();
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if (tbe.NumPendingAcks == 0) {
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enqueue(triggerQueue_out, TriggerMsg, 1) {
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out_msg.addr := address;
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out_msg.Type := TriggerType:AcksComplete;
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}
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}
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probe_dests.remove(in_msg.Requestor);
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if (probe_dests.count() > 0) {
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enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) {
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out_msg.addr := address;
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out_msg.Type := ProbeRequestType:PrbInv;
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out_msg.ReturnData := true;
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out_msg.MessageSize := MessageSizeType:Control;
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out_msg.Destination := probe_dests;
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tbe.NumPendingAcks := out_msg.Destination.count();
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DPRINTF(RubySlicc, "%s\n", out_msg);
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APPEND_TRANSITION_COMMENT(" dc: Acks remaining: ");
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APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
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tbe.ProbeRequestStartTime := curCycle();
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assert(out_msg.Destination.count() > 0);
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}
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}
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if (probe_dests.count() == 0) {
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enqueue(triggerQueue_out, TriggerMsg, 1) {
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out_msg.addr := address;
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out_msg.Type := TriggerType:AcksComplete;
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}
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DPRINTF(RubySlicc, "%s\n", out_msg);
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APPEND_TRANSITION_COMMENT(" dc: Acks remaining: ");
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APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
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tbe.ProbeRequestStartTime := curCycle();
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assert(out_msg.Destination.count() > 0);
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}
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}
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}
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action(dc_probeInvCoreData, "dc", desc="probe inv cores, return data") {
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peek(requestNetwork_in, CPURequestMsg) {
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enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) {
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out_msg.addr := address;
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out_msg.Type := ProbeRequestType:PrbInv;
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out_msg.ReturnData := true;
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out_msg.MessageSize := MessageSizeType:Control;
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NetDest probe_dests;
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// Add relevant machine types based on CPUonly, GPUonly and noTCCdir:
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// CPUonly && GPUonly -> Invalid
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// CPUonly && !GPUonly -> Add CorePairs
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// !CPUonly && GPUonly -> Add TCCs or TCC dirs if no write conflict
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// !CPUonly && !GPUonly -> Add CorePairs and TCCs or TCC dirs
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// if no write conflict
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if (CPUonly) {
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assert(!GPUonly);
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probe_dests.broadcast(MachineType:CorePair);
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} else {
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// CPU + GPU system
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if (!GPUonly) {
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// won't be realistic for multisocket
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out_msg.Destination.broadcast(MachineType:CorePair);
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probe_dests.broadcast(MachineType:CorePair);
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}
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// add relevant TCC node to list. This replaces all TCPs and SQCs
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if (((in_msg.Type == CoherenceRequestType:WriteThrough ||
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in_msg.Type == CoherenceRequestType:Atomic) &&
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in_msg.NoWriteConflict) ||
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CPUonly) {
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} else if (noTCCdir) {
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
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} else {
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out_msg.Destination.add(mapAddressToRange(address,
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MachineType:TCCdir,
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TCC_select_low_bit, TCC_select_num_bits));
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}
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out_msg.Destination.remove(in_msg.Requestor);
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tbe.NumPendingAcks := out_msg.Destination.count();
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if (tbe.NumPendingAcks == 0) {
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enqueue(triggerQueue_out, TriggerMsg, 1) {
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out_msg.addr := address;
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out_msg.Type := TriggerType:AcksComplete;
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// CPU + GPU or GPU only system
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if ((in_msg.Type != CoherenceRequestType:WriteThrough &&
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in_msg.Type != CoherenceRequestType:Atomic) ||
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!in_msg.NoWriteConflict) {
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if (noTCCdir) {
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probe_dests.add(mapAddressToRange(address, MachineType:TCC,
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TCC_select_low_bit,
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TCC_select_num_bits));
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} else {
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probe_dests.add(mapAddressToRange(address, MachineType:TCCdir,
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TCC_select_low_bit,
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TCC_select_num_bits));
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}
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}
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DPRINTF(RubySlicc, "%s\n", out_msg);
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APPEND_TRANSITION_COMMENT(" dc: Acks remaining: ");
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APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
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tbe.ProbeRequestStartTime := curCycle();
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assert(out_msg.Destination.count() > 0);
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}
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probe_dests.remove(in_msg.Requestor);
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if (probe_dests.count() > 0) {
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enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) {
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out_msg.addr := address;
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out_msg.Type := ProbeRequestType:PrbInv;
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out_msg.ReturnData := true;
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out_msg.MessageSize := MessageSizeType:Control;
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out_msg.Destination := probe_dests;
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tbe.NumPendingAcks := out_msg.Destination.count();
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DPRINTF(RubySlicc, "%s\n", out_msg);
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APPEND_TRANSITION_COMMENT(" dc: Acks remaining: ");
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APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
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tbe.ProbeRequestStartTime := curCycle();
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assert(out_msg.Destination.count() > 0);
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}
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}
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if (probe_dests.count() == 0) {
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enqueue(triggerQueue_out, TriggerMsg, 1) {
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out_msg.addr := address;
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out_msg.Type := TriggerType:AcksComplete;
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}
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}
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}
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}
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action(scd_probeShrCoreDataForDma, "dsc", desc="probe shared cores, return data for DMA") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) {
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out_msg.addr := address;
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out_msg.Type := ProbeRequestType:PrbDowngrade;
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out_msg.ReturnData := true;
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out_msg.MessageSize := MessageSizeType:Control;
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NetDest probe_dests;
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// Add relevant machine types based on CPUonly, GPUonly and noTCCdir:
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// CPUonly && GPUonly -> Invalid
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// CPUonly && !GPUonly -> Add CorePairs
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// !CPUonly && GPUonly -> Add TCCs or TCC dirs
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// !CPUonly && !GPUonly -> Add CorePairs and TCCs or TCC dirs
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if (CPUonly) {
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assert(!GPUonly);
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probe_dests.broadcast(MachineType:CorePair);
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} else {
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// CPU + GPU system
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if (!GPUonly) {
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out_msg.Destination.broadcast(MachineType:CorePair);
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probe_dests.broadcast(MachineType:CorePair);
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}
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// add relevant TCC node to the list. This replaces all TCPs and SQCs
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if (noTCCdir || CPUonly) {
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//Don't need to notify TCC about reads
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} else {
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out_msg.Destination.add(mapAddressToRange(address,
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MachineType:TCCdir,
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TCC_select_low_bit, TCC_select_num_bits));
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// CPU + GPU or GPU only system
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// We don't need to notify TCC about reads
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if (!noTCCdir) {
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probe_dests.add(mapAddressToRange(address, MachineType:TCCdir,
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TCC_select_low_bit,
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TCC_select_num_bits));
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}
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if (noTCCdir && !CPUonly) {
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
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}
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probe_dests.remove(in_msg.Requestor);
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if (probe_dests.count() > 0) {
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enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) {
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out_msg.addr := address;
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out_msg.Type := ProbeRequestType:PrbDowngrade;
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out_msg.ReturnData := true;
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out_msg.MessageSize := MessageSizeType:Control;
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out_msg.Destination := probe_dests;
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tbe.NumPendingAcks := out_msg.Destination.count();
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DPRINTF(RubySlicc, "%s\n", (out_msg));
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APPEND_TRANSITION_COMMENT(" sc: Acks remaining: ");
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APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
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tbe.ProbeRequestStartTime := curCycle();
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assert(out_msg.Destination.count() > 0);
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}
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out_msg.Destination.remove(in_msg.Requestor);
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tbe.NumPendingAcks := out_msg.Destination.count();
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if (tbe.NumPendingAcks == 0) {
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enqueue(triggerQueue_out, TriggerMsg, 1) {
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out_msg.addr := address;
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out_msg.Type := TriggerType:AcksComplete;
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}
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}
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if (probe_dests.count() == 0) {
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enqueue(triggerQueue_out, TriggerMsg, 1) {
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out_msg.addr := address;
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out_msg.Type := TriggerType:AcksComplete;
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}
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DPRINTF(RubySlicc, "%s\n", (out_msg));
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APPEND_TRANSITION_COMMENT(" sc: Acks remaining: ");
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APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
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tbe.ProbeRequestStartTime := curCycle();
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assert(out_msg.Destination.count() > 0);
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}
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}
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}
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action(sc_probeShrCoreData, "sc", desc="probe shared cores, return data") {
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peek(requestNetwork_in, CPURequestMsg) { // not the right network?
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enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) {
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out_msg.addr := address;
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out_msg.Type := ProbeRequestType:PrbDowngrade;
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out_msg.ReturnData := true;
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out_msg.MessageSize := MessageSizeType:Control;
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NetDest probe_dests;
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// Add relevant machine types based on CPUonly, GPUonly and noTCCdir:
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// CPUonly && GPUonly -> Invalid
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// CPUonly && !GPUonly -> Add CorePairs
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// !CPUonly && GPUonly -> Add TCCs or TCC dirs
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// !CPUonly && !GPUonly -> Add CorePairs and TCCs or TCC dirs
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if (CPUonly) {
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assert(!GPUonly);
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probe_dests.broadcast(MachineType:CorePair);
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} else {
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// CPU + GPU system
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if (!GPUonly) {
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// won't be realistic for multisocket
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out_msg.Destination.broadcast(MachineType:CorePair);
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probe_dests.broadcast(MachineType:CorePair);
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}
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// add relevant TCC node to the list. This replaces all TCPs and SQCs
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if (noTCCdir || CPUonly) {
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//Don't need to notify TCC about reads
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} else {
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out_msg.Destination.add(mapAddressToRange(address,
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MachineType:TCCdir,
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TCC_select_low_bit, TCC_select_num_bits));
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tbe.NumPendingAcks := tbe.NumPendingAcks + 1;
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// CPU + GPU or GPU only system
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// We don't need to notify TCC about reads
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if (!noTCCdir) {
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probe_dests.add(mapAddressToRange(address, MachineType:TCCdir,
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TCC_select_low_bit,
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TCC_select_num_bits));
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}
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if (noTCCdir && !CPUonly) {
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
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}
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probe_dests.remove(in_msg.Requestor);
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if (probe_dests.count() > 0) {
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enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) {
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out_msg.addr := address;
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out_msg.Type := ProbeRequestType:PrbDowngrade;
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out_msg.ReturnData := true;
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out_msg.MessageSize := MessageSizeType:Control;
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out_msg.Destination := probe_dests;
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tbe.NumPendingAcks := out_msg.Destination.count();
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DPRINTF(RubySlicc, "%s\n", (out_msg));
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APPEND_TRANSITION_COMMENT(" sc: Acks remaining: ");
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APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
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tbe.ProbeRequestStartTime := curCycle();
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assert(out_msg.Destination.count() > 0);
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}
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out_msg.Destination.remove(in_msg.Requestor);
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tbe.NumPendingAcks := out_msg.Destination.count();
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if (tbe.NumPendingAcks == 0) {
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enqueue(triggerQueue_out, TriggerMsg, 1) {
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out_msg.addr := address;
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out_msg.Type := TriggerType:AcksComplete;
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}
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}
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if (probe_dests.count() == 0) {
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enqueue(triggerQueue_out, TriggerMsg, 1) {
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out_msg.addr := address;
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out_msg.Type := TriggerType:AcksComplete;
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}
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DPRINTF(RubySlicc, "%s\n", (out_msg));
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APPEND_TRANSITION_COMMENT(" sc: Acks remaining: ");
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APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
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tbe.ProbeRequestStartTime := curCycle();
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assert(out_msg.Destination.count() > 0);
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}
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}
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}
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action(ic_probeInvCore, "ic", desc="probe invalidate core, no return data needed") {
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peek(requestNetwork_in, CPURequestMsg) { // not the right network?
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enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) {
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out_msg.addr := address;
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out_msg.Type := ProbeRequestType:PrbInv;
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out_msg.ReturnData := false;
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out_msg.MessageSize := MessageSizeType:Control;
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NetDest probe_dests;
|
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// Add relevant machine types based on CPUonly, GPUonly and noTCCdir:
|
||||
// CPUonly && GPUonly -> Invalid
|
||||
// CPUonly && !GPUonly -> Add CorePairs
|
||||
// !CPUonly && GPUonly -> Add TCCs or TCC dirs
|
||||
// !CPUonly && !GPUonly -> Add CorePairs and TCCs or TCC dirs
|
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if (CPUonly) {
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assert(!GPUonly);
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probe_dests.broadcast(MachineType:CorePair);
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} else {
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// CPU + GPU system
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if (!GPUonly) {
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// won't be realistic for multisocket
|
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out_msg.Destination.broadcast(MachineType:CorePair);
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probe_dests.broadcast(MachineType:CorePair);
|
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}
|
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|
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// add relevant TCC node to the list. This replaces all TCPs and SQCs
|
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if (noTCCdir && !CPUonly) {
|
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out_msg.Destination.add(mapAddressToRange(address,MachineType:TCC,
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TCC_select_low_bit, TCC_select_num_bits));
|
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// CPU + GPU or GPU only system
|
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if (noTCCdir) {
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probe_dests.add(mapAddressToRange(address, MachineType:TCC,
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TCC_select_low_bit,
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TCC_select_num_bits));
|
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} else {
|
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if (!noTCCdir) {
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out_msg.Destination.add(mapAddressToRange(address,
|
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MachineType:TCCdir,
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TCC_select_low_bit,
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TCC_select_num_bits));
|
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}
|
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probe_dests.add(mapAddressToRange(address, MachineType:TCCdir,
|
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TCC_select_low_bit,
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TCC_select_num_bits));
|
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}
|
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out_msg.Destination.remove(in_msg.Requestor);
|
||||
tbe.NumPendingAcks := out_msg.Destination.count();
|
||||
if (tbe.NumPendingAcks == 0) {
|
||||
enqueue(triggerQueue_out, TriggerMsg, 1) {
|
||||
out_msg.addr := address;
|
||||
out_msg.Type := TriggerType:AcksComplete;
|
||||
}
|
||||
}
|
||||
probe_dests.remove(in_msg.Requestor);
|
||||
|
||||
if (probe_dests.count() > 0) {
|
||||
enqueue(probeNetwork_out, NBProbeRequestMsg, response_latency) {
|
||||
out_msg.addr := address;
|
||||
out_msg.Type := ProbeRequestType:PrbInv;
|
||||
out_msg.ReturnData := false;
|
||||
out_msg.MessageSize := MessageSizeType:Control;
|
||||
out_msg.Destination := probe_dests;
|
||||
tbe.NumPendingAcks := out_msg.Destination.count();
|
||||
APPEND_TRANSITION_COMMENT(" ic: Acks remaining: ");
|
||||
APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
|
||||
DPRINTF(RubySlicc, "%s\n", out_msg);
|
||||
tbe.ProbeRequestStartTime := curCycle();
|
||||
assert(out_msg.Destination.count() > 0);
|
||||
}
|
||||
}
|
||||
|
||||
if (probe_dests.count() == 0) {
|
||||
enqueue(triggerQueue_out, TriggerMsg, 1) {
|
||||
out_msg.addr := address;
|
||||
out_msg.Type := TriggerType:AcksComplete;
|
||||
}
|
||||
APPEND_TRANSITION_COMMENT(" ic: Acks remaining: ");
|
||||
APPEND_TRANSITION_COMMENT(tbe.NumPendingAcks);
|
||||
DPRINTF(RubySlicc, "%s\n", out_msg);
|
||||
tbe.ProbeRequestStartTime := curCycle();
|
||||
assert(out_msg.Destination.count() > 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user