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arm: invalidate TLB miscreg cache on modification of HSCTLR

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Change-Id: I5212c91c56435fe008950ed99feacc6921609226
This commit is contained in:
Dylan Johnson
2016-08-02 10:38:01 +01:00
parent e727a0eeaa
commit 4fbf40daab
1 changed files with 2 additions and 1 deletions
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src/arch/arm/isa.cc
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2015 ARM Limited
* Copyright (c) 2010-2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1629,6 +1629,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
case MISCREG_TCR_EL3:
case MISCREG_SCTLR_EL2:
case MISCREG_SCTLR_EL3:
case MISCREG_HSCTLR:
case MISCREG_TTBR0_EL1:
case MISCREG_TTBR1_EL1:
case MISCREG_TTBR0_EL2: