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mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher

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A recent change (https://gem5-review.googlesource.com/c/
public/gem5/+/27949) updated the ruby prefetcher name,
which breaks the use of old name in some SLICC files.
This change makes sure that the new name is used at all
places.

Issue-On: https://gem5.atlassian.net/browse/GEM5-498
Change-Id: Ic667b61eac13dc7c267cee7dce3aa970f7ae9a8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28667
Reviewed-by: Timothy Hayes <timothy.hayes@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Ayaz Akram
2020-05-04 21:11:38 -07:00
parent 38e7427ea7
commit 4f1c4147de
11 changed files with 19 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
configs/ruby/MESI_Three_Level.py
View File

@@ -121,7 +121,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
clk_domain = system.cpu[i].clk_domain
# Ruby prefetcher
prefetcher = RubyPrefetcher.Prefetcher(
prefetcher = RubyPrefetcher(
num_streams=16,
unit_filter = 256,
nonunit_filter = 256,

2
configs/ruby/MESI_Two_Level.py
View File

@@ -78,7 +78,7 @@ def create_system(options, full_system, system, dma_ports, bootmem,
start_index_bit = block_size_bits,
is_icache = False)
prefetcher = RubyPrefetcher.Prefetcher()
prefetcher = RubyPrefetcher()
# the ruby random tester reuses num_cpus to specify the
# number of cpu ports connected to the tester object, which

2
src/mem/ruby/SConscript
View File

@@ -126,7 +126,7 @@ MakeInclude('structures/CacheMemory.hh')
MakeInclude('structures/DirectoryMemory.hh')
MakeInclude('structures/PerfectCacheMemory.hh')
MakeInclude('structures/PersistentTable.hh')
MakeInclude('structures/Prefetcher.hh')
MakeInclude('structures/RubyPrefetcher.hh')
MakeInclude('structures/TBETable.hh')
MakeInclude('structures/TimerTable.hh')
MakeInclude('structures/WireBuffer.hh')

2
src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
View File

@@ -46,7 +46,7 @@ machine(MachineType:L0Cache, "MESI Directory L0 Cache")
Cycles response_latency := 2;
bool send_evictions;
Prefetcher * prefetcher;
RubyPrefetcher * prefetcher;
bool enable_prefetch := "False";
// From this node's L0 cache to the network

2
src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
View File

@@ -30,7 +30,7 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
Prefetcher * prefetcher;
RubyPrefetcher * prefetcher;
int l2_select_num_bits;
Cycles l1_request_latency := 2;
Cycles l1_response_latency := 2;

2
src/mem/ruby/protocol/RubySlicc_Types.sm
View File

@@ -246,7 +246,7 @@ structure (TimerTable, inport="yes", external = "yes") {
bool isSet(Addr);
}
structure (Prefetcher, external = "yes") {
structure (RubyPrefetcher, external = "yes") {
void observeMiss(Addr, RubyRequestType);
void observePfHit(Addr);
void observePfMiss(Addr);

4
src/mem/ruby/structures/Prefetcher.cc → src/mem/ruby/structures/RubyPrefetcher.cc
View File

@@ -38,7 +38,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/structures/Prefetcher.hh"
#include "mem/ruby/structures/RubyPrefetcher.hh"
#include "base/bitfield.hh"
#include "debug/RubyPrefetcher.hh"
@@ -46,7 +46,7 @@
#include "mem/ruby/system/RubySystem.hh"
RubyPrefetcher*
PrefetcherParams::create()
RubyPrefetcherParams::create()
{
return new RubyPrefetcher(this);
}

4
src/mem/ruby/structures/Prefetcher.hh → src/mem/ruby/structures/RubyPrefetcher.hh
View File

@@ -51,7 +51,7 @@
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/slicc_interface/RubyRequest.hh"
#include "mem/ruby/system/RubySystem.hh"
#include "params/Prefetcher.hh"
#include "params/RubyPrefetcher.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
@@ -93,7 +93,7 @@ class PrefetchEntry
class RubyPrefetcher : public SimObject
{
public:
typedef PrefetcherParams Params;
typedef RubyPrefetcherParams Params;
RubyPrefetcher(const Params *p);
~RubyPrefetcher();

10
src/mem/ruby/structures/RubyPrefetcher.py
View File

@@ -42,10 +42,10 @@ from m5.proxy import *
from m5.objects.System import System
class Prefetcher(SimObject):
type = 'Prefetcher'
class RubyPrefetcher(SimObject):
type = 'RubyPrefetcher'
cxx_class = 'RubyPrefetcher'
cxx_header = "mem/ruby/structures/Prefetcher.hh"
cxx_header = "mem/ruby/structures/RubyPrefetcher.hh"
num_streams = Param.UInt32(4,
"Number of prefetch streams to be allocated")
@@ -58,3 +58,7 @@ class Prefetcher(SimObject):
cross_page = Param.Bool(False, """True if prefetched address can be on a
page different from the observed address""")
sys = Param.System(Parent.any, "System this prefetcher belongs to")
class Prefetcher(RubyPrefetcher):
"""DEPRECATED"""
pass

2
src/mem/ruby/structures/SConscript
View File

@@ -40,6 +40,6 @@ Source('DirectoryMemory.cc')
Source('CacheMemory.cc')
Source('WireBuffer.cc')
Source('PersistentTable.cc')
Source('Prefetcher.cc')
Source('RubyPrefetcher.cc')
Source('TimerTable.cc')
Source('BankedArray.cc')

2
src/mem/slicc/symbols/StateMachine.py
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@@ -61,7 +61,7 @@ python_class_map = {
"MemoryControl": "MemoryControl",
"MessageBuffer": "MessageBuffer",
"DMASequencer": "DMASequencer",
"Prefetcher":"Prefetcher",
"RubyPrefetcher":"RubyPrefetcher",
"Cycles":"Cycles",
}