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misc: Rename Enums namespace as enums

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As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Enums became ::enums.

Change-Id: I39b5fb48817ad16abbac92f6254284b37fc90c40
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45420
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Daniel R. Carvalho
2021-05-06 16:18:58 -03:00
committed by Daniel Carvalho
parent 06fb0753fe
commit 4dd099ba3d
77 changed files with 384 additions and 381 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/cpu/base.cc
View File

@@ -316,11 +316,11 @@ BaseCPU::startup()
}
if (_switchedOut)
powerState->set(Enums::PwrState::OFF);
powerState->set(enums::PwrState::OFF);
// Assumption CPU start to operate instantaneously without any latency
if (powerState->get() == Enums::PwrState::UNDEFINED)
powerState->set(Enums::PwrState::ON);
if (powerState->get() == enums::PwrState::UNDEFINED)
powerState->set(enums::PwrState::ON);
}
@@ -461,7 +461,7 @@ BaseCPU::schedulePowerGatingEvent()
return;
}
if (powerState->get() == Enums::PwrState::CLK_GATED &&
if (powerState->get() == enums::PwrState::CLK_GATED &&
powerGatingOnIdle) {
assert(!enterPwrGatingEvent.scheduled());
// Schedule a power gating event when clock gated for the specified
@@ -490,7 +490,7 @@ BaseCPU::activateContext(ThreadID thread_num)
if (enterPwrGatingEvent.scheduled())
deschedule(enterPwrGatingEvent);
// For any active thread running, update CPU power state to active (ON)
powerState->set(Enums::PwrState::ON);
powerState->set(enums::PwrState::ON);
updateCycleCounters(CPU_STATE_WAKEUP);
}
@@ -511,7 +511,7 @@ BaseCPU::suspendContext(ThreadID thread_num)
updateCycleCounters(CPU_STATE_SLEEP);
// All CPU threads suspended, enter lower power state for the CPU
powerState->set(Enums::PwrState::CLK_GATED);
powerState->set(enums::PwrState::CLK_GATED);
// If pwrGatingLatency is set to 0 then this mechanism is disabled
if (powerGatingOnIdle) {
@@ -530,7 +530,7 @@ BaseCPU::haltContext(ThreadID thread_num)
void
BaseCPU::enterPwrGating(void)
{
powerState->set(Enums::PwrState::OFF);
powerState->set(enums::PwrState::OFF);
}
void
@@ -544,7 +544,7 @@ BaseCPU::switchOut()
flushTLBs();
// Go to the power gating state
powerState->set(Enums::PwrState::OFF);
powerState->set(enums::PwrState::OFF);
}
void

2
src/cpu/exetrace.cc
View File

@@ -105,7 +105,7 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
outs << " : ";
if (Debug::ExecOpClass) {
outs << Enums::OpClassStrings[inst->opClass()] << " : ";
outs << enums::OpClassStrings[inst->opClass()] << " : ";
}
if (Debug::ExecResult && !predicate) {

2
src/cpu/minor/cpu.cc
View File

@@ -99,7 +99,7 @@ MinorCPU::init()
BaseCPU::init();
if (!params().switched_out &&
system->getMemoryMode() != Enums::timing)
system->getMemoryMode() != enums::timing)
{
fatal("The Minor CPU requires the memory system to be in "
"'timing' mode.\n");

2
src/cpu/minor/cpu.hh
View File

@@ -109,7 +109,7 @@ class MinorCPU : public BaseCPU
};
/** Thread Scheduling Policy (RoundRobin, Random, etc) */
Enums::ThreadPolicy threadPolicy;
enums::ThreadPolicy threadPolicy;
protected:
/** Return a reference to the data port. */
Port &getDataPort() override;

6
src/cpu/minor/decode.cc
View File

@@ -300,13 +300,13 @@ Decode::getScheduledThread()
std::vector<ThreadID> priority_list;
switch (cpu.threadPolicy) {
case Enums::SingleThreaded:
case enums::SingleThreaded:
priority_list.push_back(0);
break;
case Enums::RoundRobin:
case enums::RoundRobin:
priority_list = cpu.roundRobinPriority(threadPriority);
break;
case Enums::Random:
case enums::Random:
priority_list = cpu.randomPriority();
break;
default:

2
src/cpu/minor/dyn_inst.cc
View File

@@ -228,7 +228,7 @@ MinorDynInst::minorTraceInst(const Named &named_object,
id, pc.instAddr(),
(staticInst->opClass() == No_OpClass ?
"(invalid)" : staticInst->disassemble(0,NULL)),
Enums::OpClassStrings[staticInst->opClass()],
enums::OpClassStrings[staticInst->opClass()],
flags.str(),
regs_str.str(),
(predictedTaken ? " predictedTaken" : ""));

14
src/cpu/minor/execute.cc
View File

@@ -163,7 +163,7 @@ Execute::Execute(const std::string &name_,
if (!found_fu) {
warn("No functional unit for OpClass %s\n",
Enums::OpClassStrings[op_class]);
enums::OpClassStrings[op_class]);
}
}
@@ -1693,12 +1693,12 @@ Execute::getCommittingThread()
std::vector<ThreadID> priority_list;
switch (cpu.threadPolicy) {
case Enums::SingleThreaded:
case enums::SingleThreaded:
return 0;
case Enums::RoundRobin:
case enums::RoundRobin:
priority_list = cpu.roundRobinPriority(commitPriority);
break;
case Enums::Random:
case enums::Random:
priority_list = cpu.randomPriority();
break;
default:
@@ -1760,12 +1760,12 @@ Execute::getIssuingThread()
std::vector<ThreadID> priority_list;
switch (cpu.threadPolicy) {
case Enums::SingleThreaded:
case enums::SingleThreaded:
return 0;
case Enums::RoundRobin:
case enums::RoundRobin:
priority_list = cpu.roundRobinPriority(issuePriority);
break;
case Enums::Random:
case enums::Random:
priority_list = cpu.randomPriority();
break;
default:

6
src/cpu/minor/fetch1.cc
View File

@@ -119,13 +119,13 @@ Fetch1::getScheduledThread()
std::vector<ThreadID> priority_list;
switch (cpu.threadPolicy) {
case Enums::SingleThreaded:
case enums::SingleThreaded:
priority_list.push_back(0);
break;
case Enums::RoundRobin:
case enums::RoundRobin:
priority_list = cpu.roundRobinPriority(threadPriority);
break;
case Enums::Random:
case enums::Random:
priority_list = cpu.randomPriority();
break;
default:

6
src/cpu/minor/fetch2.cc
View File

@@ -568,13 +568,13 @@ Fetch2::getScheduledThread()
std::vector<ThreadID> priority_list;
switch (cpu.threadPolicy) {
case Enums::SingleThreaded:
case enums::SingleThreaded:
priority_list.push_back(0);
break;
case Enums::RoundRobin:
case enums::RoundRobin:
priority_list = cpu.roundRobinPriority(threadPriority);
break;
case Enums::Random:
case enums::Random:
priority_list = cpu.randomPriority();
break;
default:

4
src/cpu/minor/stats.cc
View File

@@ -72,9 +72,9 @@ MinorStats::MinorStats(BaseCPU *base_cpu)
ipc = numInsts / base_cpu->baseStats.numCycles;
committedInstType
.init(base_cpu->numThreads, Enums::Num_OpClass)
.init(base_cpu->numThreads, enums::Num_OpClass)
.flags(Stats::total | Stats::pdf | Stats::dist);
committedInstType.ysubnames(Enums::OpClassStrings);
committedInstType.ysubnames(enums::OpClassStrings);
}
};

4
src/cpu/o3/commit.cc
View File

@@ -235,10 +235,10 @@ Commit::CommitStats::CommitStats(CPU *cpu, Commit *commit)
.flags(total);
committedInstType
.init(commit->numThreads,Enums::Num_OpClass)
.init(commit->numThreads,enums::Num_OpClass)
.flags(total | pdf | dist);
committedInstType.ysubnames(Enums::OpClassStrings);
committedInstType.ysubnames(enums::OpClassStrings);
}
void

6
src/cpu/o3/cpu.cc
View File

@@ -249,7 +249,7 @@ CPU::CPU(const O3CPUParams &params)
* 'register element'. At any point only one of them will be
* active. */
const size_t numVecs = regClasses.at(VecRegClass).size();
if (vecMode == Enums::Full) {
if (vecMode == enums::Full) {
/* Initialize the full-vector interface */
for (RegIndex ridx = 0; ridx < numVecs; ++ridx) {
RegId rid = RegId(VecRegClass, ridx);
@@ -835,7 +835,7 @@ CPU::setVectorsAsReady(ThreadID tid)
const auto &regClasses = isa[tid]->regClasses();
const size_t numVecs = regClasses.at(VecRegClass).size();
if (vecMode == Enums::Elem) {
if (vecMode == enums::Elem) {
const size_t numElems = regClasses.at(VecElemClass).size();
const size_t elemsPerVec = numElems / numVecs;
for (auto v = 0; v < numVecs; v++) {
@@ -844,7 +844,7 @@ CPU::setVectorsAsReady(ThreadID tid)
RegId(VecElemClass, v, e)));
}
}
} else if (vecMode == Enums::Full) {
} else if (vecMode == enums::Full) {
for (auto v = 0; v < numVecs; v++) {
scoreboard.setReg(commitRenameMap[tid].lookup(
RegId(VecRegClass, v)));

6
src/cpu/o3/cpu.hh
View File

@@ -331,10 +331,10 @@ class CPU : public BaseCPU
TheISA::VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
/** Returns current vector renaming mode */
Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
/** Sets the current vector renaming mode */
void vecRenameMode(Enums::VecRegRenameMode vec_mode)
void vecRenameMode(enums::VecRegRenameMode vec_mode)
{ vecMode = vec_mode; }
const TheISA::VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
@@ -492,7 +492,7 @@ class CPU : public BaseCPU
Commit commit;
/** The rename mode of the vector registers */
Enums::VecRegRenameMode vecMode;
enums::VecRegRenameMode vecMode;
/** The register file. */
PhysRegFile regFile;

6
src/cpu/o3/inst_queue.cc
View File

@@ -274,10 +274,10 @@ InstructionQueue::IQStats::IQStats(CPU *cpu, const unsigned &total_width)
}
*/
statIssuedInstType
.init(cpu->numThreads,Enums::Num_OpClass)
.init(cpu->numThreads,enums::Num_OpClass)
.flags(Stats::total | Stats::pdf | Stats::dist)
;
statIssuedInstType.ysubnames(Enums::OpClassStrings);
statIssuedInstType.ysubnames(enums::OpClassStrings);
//
// How long did instructions for a particular FU type wait prior to issue
@@ -304,7 +304,7 @@ InstructionQueue::IQStats::IQStats(CPU *cpu, const unsigned &total_width)
.flags(Stats::pdf | Stats::dist)
;
for (int i=0; i < Num_OpClasses; ++i) {
statFuBusy.subname(i, Enums::OpClassStrings[i]);
statFuBusy.subname(i, enums::OpClassStrings[i]);
}
fuBusy

2
src/cpu/o3/regfile.cc
View File

@@ -162,7 +162,7 @@ PhysRegFile::initFreeList(UnifiedFreeList *freeList)
/* depending on the mode we add the vector registers as whole units or
* as different elements. */
if (vecMode == Enums::Full)
if (vecMode == enums::Full)
freeList->addRegs(vecRegIds.begin(), vecRegIds.end());
else
freeList->addRegs(vecElemIds.begin(), vecElemIds.end());

2
src/cpu/o3/regfile.hh
View File

@@ -65,7 +65,7 @@ class PhysRegFile
private:
using PhysIds = std::vector<PhysRegId>;
using VecMode = Enums::VecRegRenameMode;
using VecMode = enums::VecRegRenameMode;
public:
using IdRange = std::pair<PhysIds::iterator,
PhysIds::iterator>;

12
src/cpu/o3/rename_map.cc
View File

@@ -125,7 +125,7 @@ UnifiedRenameMap::init(const BaseISA::RegClasses &regClasses,
void
UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList)
{
if (vecMode == Enums::Elem) {
if (vecMode == enums::Elem) {
/* The free list should currently be tracking full registers. */
panic_if(freeList->hasFreeVecElems(),
@@ -141,7 +141,7 @@ UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList)
freeList->addRegs(range.first, range.second);
}
} else if (vecMode == Enums::Full) {
} else if (vecMode == enums::Full) {
/* The free list should currently be tracking register elems. */
panic_if(freeList->hasFreeVecRegs(),
@@ -162,10 +162,10 @@ UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList)
void
UnifiedRenameMap::switchMode(VecMode newVecMode)
{
if (newVecMode == Enums::Elem && vecMode == Enums::Full) {
if (newVecMode == enums::Elem && vecMode == enums::Full) {
/* Switch to vector element rename mode. */
vecMode = Enums::Elem;
vecMode = enums::Elem;
/* Split the mapping of each arch reg. */
int vec_idx = 0;
@@ -180,10 +180,10 @@ UnifiedRenameMap::switchMode(VecMode newVecMode)
vec_idx++;
}
} else if (newVecMode == Enums::Full && vecMode == Enums::Elem) {
} else if (newVecMode == enums::Full && vecMode == enums::Elem) {
/* Switch to full vector register rename mode. */
vecMode = Enums::Full;
vecMode = enums::Full;
/* To rebuild the arch regs we take the easy road:
* 1.- Stitch the elems together into vectors.

18
src/cpu/o3/rename_map.hh
View File

@@ -189,7 +189,7 @@ class UnifiedRenameMap
/** The predicate register rename map */
SimpleRenameMap predMap;
using VecMode = Enums::VecRegRenameMode;
using VecMode = enums::VecRegRenameMode;
VecMode vecMode;
/**
@@ -228,10 +228,10 @@ class UnifiedRenameMap
case FloatRegClass:
return floatMap.rename(arch_reg);
case VecRegClass:
assert(vecMode == Enums::Full);
assert(vecMode == enums::Full);
return vecMap.rename(arch_reg);
case VecElemClass:
assert(vecMode == Enums::Elem);
assert(vecMode == enums::Elem);
return vecElemMap.rename(arch_reg);
case VecPredRegClass:
return predMap.rename(arch_reg);
@@ -270,11 +270,11 @@ class UnifiedRenameMap
return floatMap.lookup(arch_reg);
case VecRegClass:
assert(vecMode == Enums::Full);
assert(vecMode == enums::Full);
return vecMap.lookup(arch_reg);
case VecElemClass:
assert(vecMode == Enums::Elem);
assert(vecMode == enums::Elem);
return vecElemMap.lookup(arch_reg);
case VecPredRegClass:
@@ -314,11 +314,11 @@ class UnifiedRenameMap
return floatMap.setEntry(arch_reg, phys_reg);
case VecRegClass:
assert(vecMode == Enums::Full);
assert(vecMode == enums::Full);
return vecMap.setEntry(arch_reg, phys_reg);
case VecElemClass:
assert(vecMode == Enums::Elem);
assert(vecMode == enums::Elem);
return vecElemMap.setEntry(arch_reg, phys_reg);
case VecPredRegClass:
@@ -352,7 +352,7 @@ class UnifiedRenameMap
{
return std::min({intMap.numFreeEntries(),
floatMap.numFreeEntries(),
vecMode == Enums::Full ? vecMap.numFreeEntries() :
vecMode == enums::Full ? vecMap.numFreeEntries() :
vecElemMap.numFreeEntries(),
predMap.numFreeEntries()});
}
@@ -362,7 +362,7 @@ class UnifiedRenameMap
unsigned
numFreeVecEntries() const
{
return vecMode == Enums::Full
return vecMode == enums::Full
? vecMap.numFreeEntries()
: vecElemMap.numFreeEntries();
}

110
src/cpu/op_class.hh
View File

@@ -47,61 +47,61 @@
* Do a bunch of wonky stuff to maintain backward compatability so I
* don't have to change code in a zillion places.
*/
using Enums::OpClass;
using Enums::No_OpClass;
using enums::OpClass;
using enums::No_OpClass;
static const OpClass IntAluOp = Enums::IntAlu;
static const OpClass IntMultOp = Enums::IntMult;
static const OpClass IntDivOp = Enums::IntDiv;
static const OpClass FloatAddOp = Enums::FloatAdd;
static const OpClass FloatCmpOp = Enums::FloatCmp;
static const OpClass FloatCvtOp = Enums::FloatCvt;
static const OpClass FloatMultOp = Enums::FloatMult;
static const OpClass FloatMultAccOp = Enums::FloatMultAcc;
static const OpClass FloatDivOp = Enums::FloatDiv;
static const OpClass FloatMiscOp = Enums::FloatMisc;
static const OpClass FloatSqrtOp = Enums::FloatSqrt;
static const OpClass SimdAddOp = Enums::SimdAdd;
static const OpClass SimdAddAccOp = Enums::SimdAddAcc;
static const OpClass SimdAluOp = Enums::SimdAlu;
static const OpClass SimdCmpOp = Enums::SimdCmp;
static const OpClass SimdCvtOp = Enums::SimdCvt;
static const OpClass SimdMiscOp = Enums::SimdMisc;
static const OpClass SimdMultOp = Enums::SimdMult;
static const OpClass SimdMultAccOp = Enums::SimdMultAcc;
static const OpClass SimdShiftOp = Enums::SimdShift;
static const OpClass SimdShiftAccOp = Enums::SimdShiftAcc;
static const OpClass SimdDivOp = Enums::SimdDiv;
static const OpClass SimdSqrtOp = Enums::SimdSqrt;
static const OpClass SimdReduceAddOp = Enums::SimdReduceAdd;
static const OpClass SimdReduceAluOp = Enums::SimdReduceAlu;
static const OpClass SimdReduceCmpOp = Enums::SimdReduceCmp;
static const OpClass SimdFloatAddOp = Enums::SimdFloatAdd;
static const OpClass SimdFloatAluOp = Enums::SimdFloatAlu;
static const OpClass SimdFloatCmpOp = Enums::SimdFloatCmp;
static const OpClass SimdFloatCvtOp = Enums::SimdFloatCvt;
static const OpClass SimdFloatDivOp = Enums::SimdFloatDiv;
static const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc;
static const OpClass SimdFloatMultOp = Enums::SimdFloatMult;
static const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc;
static const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt;
static const OpClass SimdFloatReduceCmpOp = Enums::SimdFloatReduceCmp;
static const OpClass SimdFloatReduceAddOp = Enums::SimdFloatReduceAdd;
static const OpClass SimdAesOp = Enums::SimdAes;
static const OpClass SimdAesMixOp = Enums::SimdAesMix;
static const OpClass SimdSha1HashOp = Enums::SimdSha1Hash;
static const OpClass SimdSha1Hash2Op = Enums::SimdSha1Hash2;
static const OpClass SimdSha256HashOp = Enums::SimdSha256Hash;
static const OpClass SimdSha256Hash2Op = Enums::SimdSha256Hash2;
static const OpClass SimdShaSigma2Op = Enums::SimdShaSigma2;
static const OpClass SimdShaSigma3Op = Enums::SimdShaSigma3;
static const OpClass SimdPredAluOp = Enums::SimdPredAlu;
static const OpClass MemReadOp = Enums::MemRead;
static const OpClass MemWriteOp = Enums::MemWrite;
static const OpClass FloatMemReadOp = Enums::FloatMemRead;
static const OpClass FloatMemWriteOp = Enums::FloatMemWrite;
static const OpClass IprAccessOp = Enums::IprAccess;
static const OpClass InstPrefetchOp = Enums::InstPrefetch;
static const OpClass Num_OpClasses = Enums::Num_OpClass;
static const OpClass IntAluOp = enums::IntAlu;
static const OpClass IntMultOp = enums::IntMult;
static const OpClass IntDivOp = enums::IntDiv;
static const OpClass FloatAddOp = enums::FloatAdd;
static const OpClass FloatCmpOp = enums::FloatCmp;
static const OpClass FloatCvtOp = enums::FloatCvt;
static const OpClass FloatMultOp = enums::FloatMult;
static const OpClass FloatMultAccOp = enums::FloatMultAcc;
static const OpClass FloatDivOp = enums::FloatDiv;
static const OpClass FloatMiscOp = enums::FloatMisc;
static const OpClass FloatSqrtOp = enums::FloatSqrt;
static const OpClass SimdAddOp = enums::SimdAdd;
static const OpClass SimdAddAccOp = enums::SimdAddAcc;
static const OpClass SimdAluOp = enums::SimdAlu;
static const OpClass SimdCmpOp = enums::SimdCmp;
static const OpClass SimdCvtOp = enums::SimdCvt;
static const OpClass SimdMiscOp = enums::SimdMisc;
static const OpClass SimdMultOp = enums::SimdMult;
static const OpClass SimdMultAccOp = enums::SimdMultAcc;
static const OpClass SimdShiftOp = enums::SimdShift;
static const OpClass SimdShiftAccOp = enums::SimdShiftAcc;
static const OpClass SimdDivOp = enums::SimdDiv;
static const OpClass SimdSqrtOp = enums::SimdSqrt;
static const OpClass SimdReduceAddOp = enums::SimdReduceAdd;
static const OpClass SimdReduceAluOp = enums::SimdReduceAlu;
static const OpClass SimdReduceCmpOp = enums::SimdReduceCmp;
static const OpClass SimdFloatAddOp = enums::SimdFloatAdd;
static const OpClass SimdFloatAluOp = enums::SimdFloatAlu;
static const OpClass SimdFloatCmpOp = enums::SimdFloatCmp;
static const OpClass SimdFloatCvtOp = enums::SimdFloatCvt;
static const OpClass SimdFloatDivOp = enums::SimdFloatDiv;
static const OpClass SimdFloatMiscOp = enums::SimdFloatMisc;
static const OpClass SimdFloatMultOp = enums::SimdFloatMult;
static const OpClass SimdFloatMultAccOp = enums::SimdFloatMultAcc;
static const OpClass SimdFloatSqrtOp = enums::SimdFloatSqrt;
static const OpClass SimdFloatReduceCmpOp = enums::SimdFloatReduceCmp;
static const OpClass SimdFloatReduceAddOp = enums::SimdFloatReduceAdd;
static const OpClass SimdAesOp = enums::SimdAes;
static const OpClass SimdAesMixOp = enums::SimdAesMix;
static const OpClass SimdSha1HashOp = enums::SimdSha1Hash;
static const OpClass SimdSha1Hash2Op = enums::SimdSha1Hash2;
static const OpClass SimdSha256HashOp = enums::SimdSha256Hash;
static const OpClass SimdSha256Hash2Op = enums::SimdSha256Hash2;
static const OpClass SimdShaSigma2Op = enums::SimdShaSigma2;
static const OpClass SimdShaSigma3Op = enums::SimdShaSigma3;
static const OpClass SimdPredAluOp = enums::SimdPredAlu;
static const OpClass MemReadOp = enums::MemRead;
static const OpClass MemWriteOp = enums::MemWrite;
static const OpClass FloatMemReadOp = enums::FloatMemRead;
static const OpClass FloatMemWriteOp = enums::FloatMemWrite;
static const OpClass IprAccessOp = enums::IprAccess;
static const OpClass InstPrefetchOp = enums::InstPrefetch;
static const OpClass Num_OpClasses = enums::Num_OpClass;
#endif // __CPU__OP_CLASS_HH__

4
src/cpu/simple/exec_context.hh
View File

@@ -165,11 +165,11 @@ class SimpleExecContext : public ExecContext
.prereq(dcacheStallCycles);
statExecutedInstType
.init(Enums::Num_OpClass)
.init(enums::Num_OpClass)
.flags(Stats::total | Stats::pdf | Stats::dist);
for (unsigned i = 0; i < Num_OpClasses; ++i) {
statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
statExecutedInstType.subname(i, enums::OpClassStrings[i]);
}
idleFraction = Stats::constant(1.0) - notIdleFraction;

8
src/cpu/testers/traffic_gen/base.cc
View File

@@ -414,7 +414,7 @@ BaseTrafficGen::createDram(Tick duration,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks,
unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks)
{
return std::shared_ptr<BaseGen>(new DramGen(*this, requestorId,
@@ -439,7 +439,7 @@ BaseTrafficGen::createDramRot(Tick duration,
unsigned int page_size,
unsigned int nbr_of_banks,
unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
{
@@ -473,7 +473,7 @@ BaseTrafficGen::createHybrid(Tick duration,
unsigned int buffer_size_nvm,
unsigned int nbr_of_banks_nvm,
unsigned int nbr_of_banks_util_nvm,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks_dram,
unsigned int nbr_of_ranks_nvm,
uint8_t nvm_percent)
@@ -508,7 +508,7 @@ BaseTrafficGen::createNvm(Tick duration,
unsigned int num_seq_pkts, unsigned int buffer_size,
unsigned int nbr_of_banks,
unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks)
{
return std::shared_ptr<BaseGen>(new NvmGen(*this, requestorId,

8
src/cpu/testers/traffic_gen/base.hh
View File

@@ -276,7 +276,7 @@ class BaseTrafficGen : public ClockedObject
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks, unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks);
std::shared_ptr<BaseGen> createDramRot(
@@ -286,7 +286,7 @@ class BaseTrafficGen : public ClockedObject
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks, unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank);
@@ -300,7 +300,7 @@ class BaseTrafficGen : public ClockedObject
unsigned int nbr_of_banks_dram, unsigned int nbr_of_banks_util_dram,
unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm,
unsigned int nbr_of_banks_nvm, unsigned int nbr_of_banks_util_nvm,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks_dram,
unsigned int nbr_of_ranks_nvm,
uint8_t nvm_percent);
@@ -312,7 +312,7 @@ class BaseTrafficGen : public ClockedObject
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int buffer_size,
unsigned int nbr_of_banks, unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks);
std::shared_ptr<BaseGen> createStrided(

14
src/cpu/testers/traffic_gen/dram_gen.cc
View File

@@ -53,7 +53,7 @@ DramGen::DramGen(SimObject &obj,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM,
unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks)
: RandomGen(obj, requestor_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
@@ -105,13 +105,13 @@ DramGen::getNextPacket()
} else {
// increment the column by one
if (addrMapping == Enums::RoRaBaCoCh ||
addrMapping == Enums::RoRaBaChCo)
if (addrMapping == enums::RoRaBaCoCh ||
addrMapping == enums::RoRaBaChCo)
// Simply increment addr by blocksize to increment
// the column by one
addr += blocksize;
else if (addrMapping == Enums::RoCoRaBaCh) {
else if (addrMapping == enums::RoCoRaBaCh) {
// Explicity increment the column bits
unsigned int new_col = ((addr / blocksize /
nbrOfBanksDRAM / nbrOfRanks) %
@@ -166,8 +166,8 @@ DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
unsigned int new_col =
random_mt.random<unsigned int>(0, columns_per_page - numSeqPkts);
if (addrMapping == Enums::RoRaBaCoCh ||
addrMapping == Enums::RoRaBaChCo) {
if (addrMapping == enums::RoRaBaCoCh ||
addrMapping == enums::RoRaBaChCo) {
// Block bits, then page bits, then bank bits, then rank bits
replaceBits(addr, blockBits + pageBits + bankBits - 1,
blockBits + pageBits, new_bank);
@@ -176,7 +176,7 @@ DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
replaceBits(addr, blockBits + pageBits + bankBits +rankBits - 1,
blockBits + pageBits + bankBits, new_rank);
}
} else if (addrMapping == Enums::RoCoRaBaCh) {
} else if (addrMapping == enums::RoCoRaBaCh) {
// Block bits, then bank bits, then rank bits, then page bits
replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank);
replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,

4
src/cpu/testers/traffic_gen/dram_gen.hh
View File

@@ -90,7 +90,7 @@ class DramGen : public RandomGen
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks);
PacketPtr getNextPacket();
@@ -136,7 +136,7 @@ class DramGen : public RandomGen
const unsigned int nbrOfBanksUtil;
/** Address mapping to be used */
Enums::AddrMap addrMapping;
enums::AddrMap addrMapping;
/** Number of rank bits in DRAM address*/
const unsigned int rankBits;

6
src/cpu/testers/traffic_gen/dram_rot_gen.cc
View File

@@ -98,13 +98,13 @@ DramRotGen::getNextPacket()
} else {
// increment the column by one
if (addrMapping == Enums::RoRaBaCoCh ||
addrMapping == Enums::RoRaBaChCo)
if (addrMapping == enums::RoRaBaCoCh ||
addrMapping == enums::RoRaBaChCo)
// Simply increment addr by blocksize to
// increment the column by one
addr += blocksize;
else if (addrMapping == Enums::RoCoRaBaCh) {
else if (addrMapping == enums::RoCoRaBaCh) {
// Explicity increment the column bits
unsigned int new_col = ((addr / blocksize /

2
src/cpu/testers/traffic_gen/dram_rot_gen.hh
View File

@@ -89,7 +89,7 @@ class DramRotGen : public DramGen
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int page_size,
unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks,
unsigned int max_seq_count_per_rank)
: DramGen(obj, requestor_id, _duration, start_addr, end_addr,

14
src/cpu/testers/traffic_gen/hybrid_gen.cc
View File

@@ -59,7 +59,7 @@ HybridGen::HybridGen(SimObject &obj,
unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm,
unsigned int nbr_of_banks_nvm,
unsigned int nbr_of_banks_util_nvm,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks_dram,
unsigned int nbr_of_ranks_nvm,
uint8_t nvm_percent)
@@ -197,13 +197,13 @@ HybridGen::getNextPacket()
} else {
// increment the column by one
if (addrMapping == Enums::RoRaBaCoCh ||
addrMapping == Enums::RoRaBaChCo)
if (addrMapping == enums::RoRaBaCoCh ||
addrMapping == enums::RoRaBaChCo)
// Simply increment addr by blocksize to increment
// the column by one
addr += blocksize;
else if (addrMapping == Enums::RoCoRaBaCh) {
else if (addrMapping == enums::RoCoRaBaCh) {
// Explicity increment the column bits
unsigned int new_col = ((addr / blocksize /
nbrOfBanks / nbrOfRanks) %
@@ -258,8 +258,8 @@ HybridGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
unsigned int new_col =
random_mt.random<unsigned int>(0, burst_per_page - numSeqPkts);
if (addrMapping == Enums::RoRaBaCoCh ||
addrMapping == Enums::RoRaBaChCo) {
if (addrMapping == enums::RoRaBaCoCh ||
addrMapping == enums::RoRaBaChCo) {
// Block bits, then page bits, then bank bits, then rank bits
replaceBits(addr, blockBits + pageBits + bankBits - 1,
blockBits + pageBits, new_bank);
@@ -268,7 +268,7 @@ HybridGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
replaceBits(addr, blockBits + pageBits + bankBits +rankBits - 1,
blockBits + pageBits + bankBits, new_rank);
}
} else if (addrMapping == Enums::RoCoRaBaCh) {
} else if (addrMapping == enums::RoCoRaBaCh) {
// Block bits, then bank bits, then rank bits, then page bits
replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank);
replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1,

4
src/cpu/testers/traffic_gen/hybrid_gen.hh
View File

@@ -106,7 +106,7 @@ class HybridGen : public BaseGen
unsigned int nbr_of_banks_dram, unsigned int nbr_of_banks_util_dram,
unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm,
unsigned int nbr_of_banks_nvm, unsigned int nbr_of_banks_util_nvm,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks_dram,
unsigned int nbr_of_ranks_nvm,
uint8_t nvm_percent);
@@ -204,7 +204,7 @@ class HybridGen : public BaseGen
const unsigned int nbrOfBanksUtilNvm;
/** Address mapping to be used */
Enums::AddrMap addrMapping;
enums::AddrMap addrMapping;
/** Number of ranks to be utilized for a given configuration */
const unsigned int nbrOfRanksDram;

14
src/cpu/testers/traffic_gen/nvm_gen.cc
View File

@@ -53,7 +53,7 @@ NvmGen::NvmGen(SimObject &obj,
unsigned int num_seq_pkts, unsigned int buffer_size,
unsigned int nbr_of_banks,
unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks)
: RandomGen(obj, requestor_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
@@ -105,13 +105,13 @@ NvmGen::getNextPacket()
} else {
// increment the column by one
if (addrMapping == Enums::RoRaBaCoCh ||
addrMapping == Enums::RoRaBaChCo)
if (addrMapping == enums::RoRaBaCoCh ||
addrMapping == enums::RoRaBaChCo)
// Simply increment addr by blocksize to increment
// the column by one
addr += blocksize;
else if (addrMapping == Enums::RoCoRaBaCh) {
else if (addrMapping == enums::RoCoRaBaCh) {
// Explicity increment the column bits
unsigned int new_col = ((addr / blocksize /
nbrOfBanksNVM / nbrOfRanks) %
@@ -161,8 +161,8 @@ NvmGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
unsigned int new_col =
random_mt.random<unsigned int>(0, burst_per_buffer - numSeqPkts);
if (addrMapping == Enums::RoRaBaCoCh ||
addrMapping == Enums::RoRaBaChCo) {
if (addrMapping == enums::RoRaBaCoCh ||
addrMapping == enums::RoRaBaChCo) {
// Block bits, then buffer bits, then bank bits, then rank bits
replaceBits(addr, blockBits + bufferBits + bankBits - 1,
blockBits + bufferBits, new_bank);
@@ -172,7 +172,7 @@ NvmGen::genStartAddr(unsigned int new_bank, unsigned int new_rank)
rankBits - 1, blockBits + bufferBits + bankBits,
new_rank);
}
} else if (addrMapping == Enums::RoCoRaBaCh) {
} else if (addrMapping == enums::RoCoRaBaCh) {
// Block bits, then bank bits, then rank bits, then buffer bits
replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank);
replaceBits(addr, blockBits + bankBits + rankBits + bufferBits - 1,

4
src/cpu/testers/traffic_gen/nvm_gen.hh
View File

@@ -90,7 +90,7 @@ class NvmGen : public RandomGen
uint8_t read_percent, Addr data_limit,
unsigned int num_seq_pkts, unsigned int buffer_size,
unsigned int nbr_of_banks, unsigned int nbr_of_banks_util,
Enums::AddrMap addr_mapping,
enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks);
PacketPtr getNextPacket();
@@ -136,7 +136,7 @@ class NvmGen : public RandomGen
const unsigned int nbrOfBanksUtil;
/** Address mapping to be used */
Enums::AddrMap addrMapping;
enums::AddrMap addrMapping;
/** Number of rank bits in NVM address*/
const unsigned int rankBits;

4
src/cpu/testers/traffic_gen/traffic_gen.cc
View File

@@ -220,8 +220,8 @@ TrafficGen::parseConfig()
is >> stride_size >> page_size >> nbr_of_banks >>
nbr_of_banks_util >> _addr_mapping >>
nbr_of_ranks;
Enums::AddrMap addr_mapping =
static_cast<Enums::AddrMap>(_addr_mapping);
enums::AddrMap addr_mapping =
static_cast<enums::AddrMap>(_addr_mapping);
if (stride_size > page_size)
warn("Memory generator stride size (%d) is greater"

40
src/cpu/timing_expr.cc
View File

@@ -90,23 +90,23 @@ uint64_t TimingExprUn::eval(TimingExprEvalContext &context)
uint64_t ret = 0;
switch (op) {
case Enums::timingExprSizeInBits:
case enums::timingExprSizeInBits:
if (arg_value == 0)
ret = 0;
else
ret = ceilLog2(arg_value);
break;
case Enums::timingExprNot:
case enums::timingExprNot:
ret = arg_value != 0;
break;
case Enums::timingExprInvert:
case enums::timingExprInvert:
ret = ~arg_value;
break;
case Enums::timingExprSignExtend32To64:
case enums::timingExprSignExtend32To64:
ret = static_cast<int64_t>(
static_cast<int32_t>(arg_value));
break;
case Enums::timingExprAbs:
case enums::timingExprAbs:
if (static_cast<int64_t>(arg_value) < 0)
ret = -arg_value;
else
@@ -126,59 +126,59 @@ uint64_t TimingExprBin::eval(TimingExprEvalContext &context)
uint64_t ret = 0;
switch (op) {
case Enums::timingExprAdd:
case enums::timingExprAdd:
ret = left_value + right_value;
break;
case Enums::timingExprSub:
case enums::timingExprSub:
ret = left_value - right_value;
break;
case Enums::timingExprUMul:
case enums::timingExprUMul:
ret = left_value * right_value;
break;
case Enums::timingExprUDiv:
case enums::timingExprUDiv:
if (right_value != 0) {
ret = left_value / right_value;
}
break;
case Enums::timingExprUCeilDiv:
case enums::timingExprUCeilDiv:
if (right_value != 0) {
ret = (left_value + (right_value - 1)) / right_value;
}
break;
case Enums::timingExprSMul:
case enums::timingExprSMul:
ret = static_cast<int64_t>(left_value) *
static_cast<int64_t>(right_value);
break;
case Enums::timingExprSDiv:
case enums::timingExprSDiv:
if (right_value != 0) {
ret = static_cast<int64_t>(left_value) /
static_cast<int64_t>(right_value);
}
break;
case Enums::timingExprEqual:
case enums::timingExprEqual:
ret = left_value == right_value;
break;
case Enums::timingExprNotEqual:
case enums::timingExprNotEqual:
ret = left_value != right_value;
break;
case Enums::timingExprULessThan:
case enums::timingExprULessThan:
ret = left_value < right_value;
break;
case Enums::timingExprUGreaterThan:
case enums::timingExprUGreaterThan:
ret = left_value > right_value;
break;
case Enums::timingExprSLessThan:
case enums::timingExprSLessThan:
ret = static_cast<int64_t>(left_value) <
static_cast<int64_t>(right_value);
break;
case Enums::timingExprSGreaterThan:
case enums::timingExprSGreaterThan:
ret = static_cast<int64_t>(left_value) >
static_cast<int64_t>(right_value);
break;
case Enums::timingExprAnd:
case enums::timingExprAnd:
ret = (left_value != 0) && (right_value != 0);
break;
case Enums::timingExprOr:
case enums::timingExprOr:
ret = (left_value != 0) || (right_value != 0);
break;
default:

4
src/cpu/timing_expr.hh
View File

@@ -165,7 +165,7 @@ class TimingExprRef : public TimingExpr
class TimingExprUn : public TimingExpr
{
public:
Enums::TimingExprOp op;
enums::TimingExprOp op;
TimingExpr *arg;
TimingExprUn(const TimingExprUnParams &params) :
@@ -180,7 +180,7 @@ class TimingExprUn : public TimingExpr
class TimingExprBin : public TimingExpr
{
public:
Enums::TimingExprOp op;
enums::TimingExprOp op;
TimingExpr *left;
TimingExpr *right;