From 4dd099ba3d541da2df2e2132ec65e320d7e16572 Mon Sep 17 00:00:00 2001 From: "Daniel R. Carvalho" Date: Thu, 6 May 2021 16:18:58 -0300 Subject: [PATCH] misc: Rename Enums namespace as enums As part of recent decisions regarding namespace naming conventions, all namespaces will be changed to snake case. ::Enums became ::enums. Change-Id: I39b5fb48817ad16abbac92f6254284b37fc90c40 Signed-off-by: Daniel R. Carvalho Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45420 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/arch/amdgpu/gcn3/ast_interpreter.py | 2 +- src/arch/amdgpu/gcn3/insts/instructions.cc | 64 +++++------ src/arch/arm/decoder.hh | 2 +- src/arch/arm/isa.cc | 2 +- src/arch/arm/isa.hh | 12 +- src/arch/generic/isa.hh | 6 +- src/arch/x86/bios/intelmp.hh | 6 +- src/base/imgwriter.cc | 8 +- src/base/imgwriter.hh | 2 +- src/base/vnc/vncinput.hh | 2 +- src/cpu/base.cc | 16 +-- src/cpu/exetrace.cc | 2 +- src/cpu/minor/cpu.cc | 2 +- src/cpu/minor/cpu.hh | 2 +- src/cpu/minor/decode.cc | 6 +- src/cpu/minor/dyn_inst.cc | 2 +- src/cpu/minor/execute.cc | 14 +-- src/cpu/minor/fetch1.cc | 6 +- src/cpu/minor/fetch2.cc | 6 +- src/cpu/minor/stats.cc | 4 +- src/cpu/o3/commit.cc | 4 +- src/cpu/o3/cpu.cc | 6 +- src/cpu/o3/cpu.hh | 6 +- src/cpu/o3/inst_queue.cc | 6 +- src/cpu/o3/regfile.cc | 2 +- src/cpu/o3/regfile.hh | 2 +- src/cpu/o3/rename_map.cc | 12 +- src/cpu/o3/rename_map.hh | 18 +-- src/cpu/op_class.hh | 110 +++++++++---------- src/cpu/simple/exec_context.hh | 4 +- src/cpu/testers/traffic_gen/base.cc | 8 +- src/cpu/testers/traffic_gen/base.hh | 8 +- src/cpu/testers/traffic_gen/dram_gen.cc | 14 +-- src/cpu/testers/traffic_gen/dram_gen.hh | 4 +- src/cpu/testers/traffic_gen/dram_rot_gen.cc | 6 +- src/cpu/testers/traffic_gen/dram_rot_gen.hh | 2 +- src/cpu/testers/traffic_gen/hybrid_gen.cc | 14 +-- src/cpu/testers/traffic_gen/hybrid_gen.hh | 4 +- src/cpu/testers/traffic_gen/nvm_gen.cc | 14 +-- src/cpu/testers/traffic_gen/nvm_gen.hh | 4 +- src/cpu/testers/traffic_gen/traffic_gen.cc | 4 +- src/cpu/timing_expr.cc | 40 +++---- src/cpu/timing_expr.hh | 4 +- src/dev/arm/flash_device.cc | 2 +- src/dev/arm/flash_device.hh | 2 +- src/dev/arm/fvp_base_pwr_ctrl.cc | 4 +- src/dev/arm/gpu_nomali.cc | 10 +- src/dev/arm/hdlcd.hh | 2 +- src/dev/arm/pci_host.cc | 6 +- src/dev/arm/pci_host.hh | 2 +- src/dev/x86/i8259.cc | 2 +- src/dev/x86/i8259.hh | 2 +- src/gpu-compute/compute_unit.cc | 42 +++---- src/gpu-compute/compute_unit.hh | 2 +- src/gpu-compute/gpu_dyn_inst.cc | 20 ++-- src/gpu-compute/gpu_dyn_inst.hh | 2 +- src/gpu-compute/gpu_static_inst.cc | 2 +- src/gpu-compute/gpu_static_inst.hh | 16 +-- src/gpu-compute/wavefront.cc | 10 +- src/mem/cache/base.cc | 2 +- src/mem/cache/base.hh | 4 +- src/mem/cache/cache.cc | 2 +- src/mem/mem_ctrl.cc | 4 +- src/mem/mem_ctrl.hh | 2 +- src/mem/mem_interface.cc | 18 +-- src/mem/mem_interface.hh | 4 +- src/mem/qos/q_policy.cc | 6 +- src/mem/ruby/network/garnet/NetworkBridge.cc | 6 +- src/python/m5/params.py | 11 +- src/sim/power/power_model.cc | 6 +- src/sim/power/power_model.hh | 2 +- src/sim/power_domain.cc | 38 +++---- src/sim/power_domain.hh | 10 +- src/sim/power_state.cc | 32 +++--- src/sim/power_state.hh | 14 +-- src/sim/system.cc | 2 +- src/sim/system.hh | 14 +-- 77 files changed, 384 insertions(+), 381 deletions(-) diff --git a/src/arch/amdgpu/gcn3/ast_interpreter.py b/src/arch/amdgpu/gcn3/ast_interpreter.py index 99ddd3c103..6bd035cf07 100644 --- a/src/arch/amdgpu/gcn3/ast_interpreter.py +++ b/src/arch/amdgpu/gcn3/ast_interpreter.py @@ -755,7 +755,7 @@ class GenOne(object): self.cg.cg_code('wf->scalarWrGmReqsInPipe--;') self.cg.cg_code('wf->scalarOutstandingReqsWrGm++;') elif is_flat_mem: - self.cg.cg_if('gpuDynInst->executedAs() == Enums::SC_GLOBAL') + self.cg.cg_if('gpuDynInst->executedAs() == enums::SC_GLOBAL') self.cg.cg_code('gpuDynInst->computeUnit()->globalMemoryPipe.') self.cg.inc_indent() self.cg.cg_code('getGMReqFIFO().push(gpuDynInst);') diff --git a/src/arch/amdgpu/gcn3/insts/instructions.cc b/src/arch/amdgpu/gcn3/insts/instructions.cc index 2761008198..0a9a966185 100644 --- a/src/arch/amdgpu/gcn3/insts/instructions.cc +++ b/src/arch/amdgpu/gcn3/insts/instructions.cc @@ -36352,7 +36352,7 @@ namespace Gcn3ISA gpuDynInst->latency.init(gpuDynInst->computeUnit()); gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod()); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -36410,7 +36410,7 @@ namespace Gcn3ISA gpuDynInst->latency.init(gpuDynInst->computeUnit()); gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod()); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -39444,7 +39444,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->rdGmReqsInPipe--; @@ -39517,7 +39517,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->rdGmReqsInPipe--; @@ -39589,7 +39589,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->rdGmReqsInPipe--; @@ -39690,7 +39690,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->rdGmReqsInPipe--; @@ -39763,7 +39763,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->rdGmReqsInPipe--; @@ -39836,7 +39836,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->rdGmReqsInPipe--; @@ -39918,7 +39918,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->rdGmReqsInPipe--; @@ -40000,7 +40000,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -40070,7 +40070,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -40141,7 +40141,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -40212,7 +40212,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -40283,7 +40283,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -40363,7 +40363,7 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe .issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -40460,10 +40460,10 @@ namespace Gcn3ISA calcAddr(gpuDynInst, addr); - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL || - gpuDynInst->executedAs() == Enums::SC_PRIVATE) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL || + gpuDynInst->executedAs() == enums::SC_PRIVATE) { // TODO: additional address computation required for scratch - panic_if(gpuDynInst->executedAs() == Enums::SC_PRIVATE, + panic_if(gpuDynInst->executedAs() == enums::SC_PRIVATE, "Flats to private aperture not tested yet\n"); gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); @@ -40582,15 +40582,15 @@ namespace Gcn3ISA } } - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL || - gpuDynInst->executedAs() == Enums::SC_PRIVATE) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL || + gpuDynInst->executedAs() == enums::SC_PRIVATE) { /** * TODO: If you encounter this panic, just remove this panic * and restart the simulation. It should just work fine but * this is to warn user that this path is never tested although * all the necessary logic is implemented */ - panic_if(gpuDynInst->executedAs() == Enums::SC_PRIVATE, + panic_if(gpuDynInst->executedAs() == enums::SC_PRIVATE, "Flats to private aperture not tested yet\n"); gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); @@ -40688,7 +40688,7 @@ namespace Gcn3ISA } } - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -40785,7 +40785,7 @@ namespace Gcn3ISA } } - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -41056,7 +41056,7 @@ namespace Gcn3ISA } } - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -41153,7 +41153,7 @@ namespace Gcn3ISA } } - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -41283,15 +41283,15 @@ namespace Gcn3ISA } } - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL || - gpuDynInst->executedAs() == Enums::SC_PRIVATE) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL || + gpuDynInst->executedAs() == enums::SC_PRIVATE) { /** * TODO: If you encounter this panic, just remove this panic * and restart the simulation. It should just work fine but * this is to warn user that this path is never tested although * all the necessary logic is implemented */ - panic_if(gpuDynInst->executedAs() == Enums::SC_PRIVATE, + panic_if(gpuDynInst->executedAs() == enums::SC_PRIVATE, "Flats to private aperture not tested yet\n"); gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); @@ -41390,7 +41390,7 @@ namespace Gcn3ISA } } - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -41489,7 +41489,7 @@ namespace Gcn3ISA } } - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -41770,7 +41770,7 @@ namespace Gcn3ISA } } - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; @@ -41870,7 +41870,7 @@ namespace Gcn3ISA } } - if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) { + if (gpuDynInst->executedAs() == enums::SC_GLOBAL) { gpuDynInst->computeUnit()->globalMemoryPipe. issueRequest(gpuDynInst); wf->wrGmReqsInPipe--; diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh index 7f63f320c9..2542f47a1c 100644 --- a/src/arch/arm/decoder.hh +++ b/src/arch/arm/decoder.hh @@ -78,7 +78,7 @@ class Decoder : public InstDecoder */ int sveLen; - Enums::DecoderFlavor decoderFlavor; + enums::DecoderFlavor decoderFlavor; /// A cache of decoded instruction objects. static GenericISA::BasicDecodeCache defaultCache; diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 69a350fbd7..08a5d66fe1 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -492,7 +492,7 @@ copyVecRegs(ThreadContext *src, ThreadContext *dest) // The way vector registers are copied (VecReg vs VecElem) is relevant // in the O3 model only. - if (src_mode == Enums::Full) { + if (src_mode == enums::Full) { for (auto idx = 0; idx < NumVecRegs; idx++) dest->setVecRegFlat(idx, src->readVecRegFlat(idx)); } else { diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index bc773f5cfd..13fa942618 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -69,7 +69,7 @@ namespace ArmISA ArmSystem *system; // Micro Architecture - const Enums::DecoderFlavor _decoderFlavor; + const enums::DecoderFlavor _decoderFlavor; /** Dummy device for to handle non-existing ISA devices */ DummyISADevice dummyDevice; @@ -874,7 +874,7 @@ namespace ArmISA void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override; - Enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; } + enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; } /** Returns true if the ISA has a GICv3 cpu interface */ bool haveGICv3CpuIfc() const @@ -886,16 +886,16 @@ namespace ArmISA return gicv3CpuInterface != nullptr; } - Enums::VecRegRenameMode + enums::VecRegRenameMode initVecRegRenameMode() const override { - return highestELIs64 ? Enums::Full : Enums::Elem; + return highestELIs64 ? enums::Full : enums::Elem; } - Enums::VecRegRenameMode + enums::VecRegRenameMode vecRegRenameMode(ThreadContext *_tc) const override { - return _tc->pcState().aarch64() ? Enums::Full : Enums::Elem; + return _tc->pcState().aarch64() ? enums::Full : enums::Elem; } PARAMS(ArmISA); diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh index 278843ebd6..5bf9928296 100644 --- a/src/arch/generic/isa.hh +++ b/src/arch/generic/isa.hh @@ -68,13 +68,13 @@ class BaseISA : public SimObject virtual bool inUserMode() const = 0; virtual void copyRegsFrom(ThreadContext *src) = 0; - virtual Enums::VecRegRenameMode + virtual enums::VecRegRenameMode initVecRegRenameMode() const { - return Enums::Full; + return enums::Full; } - virtual Enums::VecRegRenameMode + virtual enums::VecRegRenameMode vecRegRenameMode(ThreadContext *_tc) const { return initVecRegRenameMode(); diff --git a/src/arch/x86/bios/intelmp.hh b/src/arch/x86/bios/intelmp.hh index 837fc5cbc6..48ba4bba16 100644 --- a/src/arch/x86/bios/intelmp.hh +++ b/src/arch/x86/bios/intelmp.hh @@ -230,9 +230,9 @@ class IntAssignment : public BaseConfigEntry Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum); IntAssignment(const X86IntelMPBaseConfigEntryParams &p, - Enums::X86IntelMPInterruptType _interruptType, - Enums::X86IntelMPPolarity polarity, - Enums::X86IntelMPTriggerMode trigger, + enums::X86IntelMPInterruptType _interruptType, + enums::X86IntelMPPolarity polarity, + enums::X86IntelMPTriggerMode trigger, uint8_t _type, uint8_t _sourceBusID, uint8_t _sourceBusIRQ, uint8_t _destApicID, uint8_t _destApicIntIn) : diff --git a/src/base/imgwriter.cc b/src/base/imgwriter.cc index 2258e0337a..47cbcb1762 100644 --- a/src/base/imgwriter.cc +++ b/src/base/imgwriter.cc @@ -47,10 +47,10 @@ #endif std::unique_ptr -createImgWriter(Enums::ImageFormat type, const FrameBuffer *fb) +createImgWriter(enums::ImageFormat type, const FrameBuffer *fb) { switch (type) { - case Enums::Auto: + case enums::Auto: // The Auto option allows gem5 to choose automatically the // writer type, and it will choose for the best fit in // performance. @@ -59,10 +59,10 @@ createImgWriter(Enums::ImageFormat type, const FrameBuffer *fb) GEM5_FALLTHROUGH; #if HAVE_PNG - case Enums::Png: + case enums::Png: return std::unique_ptr(new PngWriter(fb)); #endif - case Enums::Bitmap: + case enums::Bitmap: return std::unique_ptr(new BmpWriter(fb)); default: warn("Invalid Image Type specified, defaulting to Bitmap\n"); diff --git a/src/base/imgwriter.hh b/src/base/imgwriter.hh index 7b288d7480..0eb30a7c7b 100644 --- a/src/base/imgwriter.hh +++ b/src/base/imgwriter.hh @@ -85,6 +85,6 @@ class ImgWriter * @return smart pointer to the allocated Image Writer */ std::unique_ptr -createImgWriter(Enums::ImageFormat type, const FrameBuffer *fb); +createImgWriter(enums::ImageFormat type, const FrameBuffer *fb); #endif //__BASE_IMGWRITER_HH__ diff --git a/src/base/vnc/vncinput.hh b/src/base/vnc/vncinput.hh index aba4ac004f..7970c8ea36 100644 --- a/src/base/vnc/vncinput.hh +++ b/src/base/vnc/vncinput.hh @@ -236,7 +236,7 @@ class VncInput : public SimObject std::unique_ptr captureImage; /** image format */ - Enums::ImageFormat imgFormat; + enums::ImageFormat imgFormat; /** Captures the current frame buffer to a file */ void captureFrameBuffer(); diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 81581ba932..21206719d5 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -316,11 +316,11 @@ BaseCPU::startup() } if (_switchedOut) - powerState->set(Enums::PwrState::OFF); + powerState->set(enums::PwrState::OFF); // Assumption CPU start to operate instantaneously without any latency - if (powerState->get() == Enums::PwrState::UNDEFINED) - powerState->set(Enums::PwrState::ON); + if (powerState->get() == enums::PwrState::UNDEFINED) + powerState->set(enums::PwrState::ON); } @@ -461,7 +461,7 @@ BaseCPU::schedulePowerGatingEvent() return; } - if (powerState->get() == Enums::PwrState::CLK_GATED && + if (powerState->get() == enums::PwrState::CLK_GATED && powerGatingOnIdle) { assert(!enterPwrGatingEvent.scheduled()); // Schedule a power gating event when clock gated for the specified @@ -490,7 +490,7 @@ BaseCPU::activateContext(ThreadID thread_num) if (enterPwrGatingEvent.scheduled()) deschedule(enterPwrGatingEvent); // For any active thread running, update CPU power state to active (ON) - powerState->set(Enums::PwrState::ON); + powerState->set(enums::PwrState::ON); updateCycleCounters(CPU_STATE_WAKEUP); } @@ -511,7 +511,7 @@ BaseCPU::suspendContext(ThreadID thread_num) updateCycleCounters(CPU_STATE_SLEEP); // All CPU threads suspended, enter lower power state for the CPU - powerState->set(Enums::PwrState::CLK_GATED); + powerState->set(enums::PwrState::CLK_GATED); // If pwrGatingLatency is set to 0 then this mechanism is disabled if (powerGatingOnIdle) { @@ -530,7 +530,7 @@ BaseCPU::haltContext(ThreadID thread_num) void BaseCPU::enterPwrGating(void) { - powerState->set(Enums::PwrState::OFF); + powerState->set(enums::PwrState::OFF); } void @@ -544,7 +544,7 @@ BaseCPU::switchOut() flushTLBs(); // Go to the power gating state - powerState->set(Enums::PwrState::OFF); + powerState->set(enums::PwrState::OFF); } void diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index f209bd41d2..cd70f1c0cf 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -105,7 +105,7 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran) outs << " : "; if (Debug::ExecOpClass) { - outs << Enums::OpClassStrings[inst->opClass()] << " : "; + outs << enums::OpClassStrings[inst->opClass()] << " : "; } if (Debug::ExecResult && !predicate) { diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc index 1c23f2dfef..02f934cd64 100644 --- a/src/cpu/minor/cpu.cc +++ b/src/cpu/minor/cpu.cc @@ -99,7 +99,7 @@ MinorCPU::init() BaseCPU::init(); if (!params().switched_out && - system->getMemoryMode() != Enums::timing) + system->getMemoryMode() != enums::timing) { fatal("The Minor CPU requires the memory system to be in " "'timing' mode.\n"); diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh index 1e84656566..c26136db36 100644 --- a/src/cpu/minor/cpu.hh +++ b/src/cpu/minor/cpu.hh @@ -109,7 +109,7 @@ class MinorCPU : public BaseCPU }; /** Thread Scheduling Policy (RoundRobin, Random, etc) */ - Enums::ThreadPolicy threadPolicy; + enums::ThreadPolicy threadPolicy; protected: /** Return a reference to the data port. */ Port &getDataPort() override; diff --git a/src/cpu/minor/decode.cc b/src/cpu/minor/decode.cc index 556bfa903c..63c1b73d27 100644 --- a/src/cpu/minor/decode.cc +++ b/src/cpu/minor/decode.cc @@ -300,13 +300,13 @@ Decode::getScheduledThread() std::vector priority_list; switch (cpu.threadPolicy) { - case Enums::SingleThreaded: + case enums::SingleThreaded: priority_list.push_back(0); break; - case Enums::RoundRobin: + case enums::RoundRobin: priority_list = cpu.roundRobinPriority(threadPriority); break; - case Enums::Random: + case enums::Random: priority_list = cpu.randomPriority(); break; default: diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc index bfd83ea1f5..f94d6c9932 100644 --- a/src/cpu/minor/dyn_inst.cc +++ b/src/cpu/minor/dyn_inst.cc @@ -228,7 +228,7 @@ MinorDynInst::minorTraceInst(const Named &named_object, id, pc.instAddr(), (staticInst->opClass() == No_OpClass ? "(invalid)" : staticInst->disassemble(0,NULL)), - Enums::OpClassStrings[staticInst->opClass()], + enums::OpClassStrings[staticInst->opClass()], flags.str(), regs_str.str(), (predictedTaken ? " predictedTaken" : "")); diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc index cf08c852e3..855614e1b4 100644 --- a/src/cpu/minor/execute.cc +++ b/src/cpu/minor/execute.cc @@ -163,7 +163,7 @@ Execute::Execute(const std::string &name_, if (!found_fu) { warn("No functional unit for OpClass %s\n", - Enums::OpClassStrings[op_class]); + enums::OpClassStrings[op_class]); } } @@ -1693,12 +1693,12 @@ Execute::getCommittingThread() std::vector priority_list; switch (cpu.threadPolicy) { - case Enums::SingleThreaded: + case enums::SingleThreaded: return 0; - case Enums::RoundRobin: + case enums::RoundRobin: priority_list = cpu.roundRobinPriority(commitPriority); break; - case Enums::Random: + case enums::Random: priority_list = cpu.randomPriority(); break; default: @@ -1760,12 +1760,12 @@ Execute::getIssuingThread() std::vector priority_list; switch (cpu.threadPolicy) { - case Enums::SingleThreaded: + case enums::SingleThreaded: return 0; - case Enums::RoundRobin: + case enums::RoundRobin: priority_list = cpu.roundRobinPriority(issuePriority); break; - case Enums::Random: + case enums::Random: priority_list = cpu.randomPriority(); break; default: diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc index 340bba544a..6be24818e6 100644 --- a/src/cpu/minor/fetch1.cc +++ b/src/cpu/minor/fetch1.cc @@ -119,13 +119,13 @@ Fetch1::getScheduledThread() std::vector priority_list; switch (cpu.threadPolicy) { - case Enums::SingleThreaded: + case enums::SingleThreaded: priority_list.push_back(0); break; - case Enums::RoundRobin: + case enums::RoundRobin: priority_list = cpu.roundRobinPriority(threadPriority); break; - case Enums::Random: + case enums::Random: priority_list = cpu.randomPriority(); break; default: diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc index 57ba03fe4a..d6c608bdaf 100644 --- a/src/cpu/minor/fetch2.cc +++ b/src/cpu/minor/fetch2.cc @@ -568,13 +568,13 @@ Fetch2::getScheduledThread() std::vector priority_list; switch (cpu.threadPolicy) { - case Enums::SingleThreaded: + case enums::SingleThreaded: priority_list.push_back(0); break; - case Enums::RoundRobin: + case enums::RoundRobin: priority_list = cpu.roundRobinPriority(threadPriority); break; - case Enums::Random: + case enums::Random: priority_list = cpu.randomPriority(); break; default: diff --git a/src/cpu/minor/stats.cc b/src/cpu/minor/stats.cc index c6cfb42605..7d2030a912 100644 --- a/src/cpu/minor/stats.cc +++ b/src/cpu/minor/stats.cc @@ -72,9 +72,9 @@ MinorStats::MinorStats(BaseCPU *base_cpu) ipc = numInsts / base_cpu->baseStats.numCycles; committedInstType - .init(base_cpu->numThreads, Enums::Num_OpClass) + .init(base_cpu->numThreads, enums::Num_OpClass) .flags(Stats::total | Stats::pdf | Stats::dist); - committedInstType.ysubnames(Enums::OpClassStrings); + committedInstType.ysubnames(enums::OpClassStrings); } }; diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc index 7f1e9ca87a..6a0f5682e2 100644 --- a/src/cpu/o3/commit.cc +++ b/src/cpu/o3/commit.cc @@ -235,10 +235,10 @@ Commit::CommitStats::CommitStats(CPU *cpu, Commit *commit) .flags(total); committedInstType - .init(commit->numThreads,Enums::Num_OpClass) + .init(commit->numThreads,enums::Num_OpClass) .flags(total | pdf | dist); - committedInstType.ysubnames(Enums::OpClassStrings); + committedInstType.ysubnames(enums::OpClassStrings); } void diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index ad0102debb..5f0d2ec587 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -249,7 +249,7 @@ CPU::CPU(const O3CPUParams ¶ms) * 'register element'. At any point only one of them will be * active. */ const size_t numVecs = regClasses.at(VecRegClass).size(); - if (vecMode == Enums::Full) { + if (vecMode == enums::Full) { /* Initialize the full-vector interface */ for (RegIndex ridx = 0; ridx < numVecs; ++ridx) { RegId rid = RegId(VecRegClass, ridx); @@ -835,7 +835,7 @@ CPU::setVectorsAsReady(ThreadID tid) const auto ®Classes = isa[tid]->regClasses(); const size_t numVecs = regClasses.at(VecRegClass).size(); - if (vecMode == Enums::Elem) { + if (vecMode == enums::Elem) { const size_t numElems = regClasses.at(VecElemClass).size(); const size_t elemsPerVec = numElems / numVecs; for (auto v = 0; v < numVecs; v++) { @@ -844,7 +844,7 @@ CPU::setVectorsAsReady(ThreadID tid) RegId(VecElemClass, v, e))); } } - } else if (vecMode == Enums::Full) { + } else if (vecMode == enums::Full) { for (auto v = 0; v < numVecs; v++) { scoreboard.setReg(commitRenameMap[tid].lookup( RegId(VecRegClass, v))); diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 41e340baba..85b20e852e 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -331,10 +331,10 @@ class CPU : public BaseCPU TheISA::VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx); /** Returns current vector renaming mode */ - Enums::VecRegRenameMode vecRenameMode() const { return vecMode; } + enums::VecRegRenameMode vecRenameMode() const { return vecMode; } /** Sets the current vector renaming mode */ - void vecRenameMode(Enums::VecRegRenameMode vec_mode) + void vecRenameMode(enums::VecRegRenameMode vec_mode) { vecMode = vec_mode; } const TheISA::VecElem& readVecElem(PhysRegIdPtr reg_idx) const; @@ -492,7 +492,7 @@ class CPU : public BaseCPU Commit commit; /** The rename mode of the vector registers */ - Enums::VecRegRenameMode vecMode; + enums::VecRegRenameMode vecMode; /** The register file. */ PhysRegFile regFile; diff --git a/src/cpu/o3/inst_queue.cc b/src/cpu/o3/inst_queue.cc index 268739be8f..4c3533af61 100644 --- a/src/cpu/o3/inst_queue.cc +++ b/src/cpu/o3/inst_queue.cc @@ -274,10 +274,10 @@ InstructionQueue::IQStats::IQStats(CPU *cpu, const unsigned &total_width) } */ statIssuedInstType - .init(cpu->numThreads,Enums::Num_OpClass) + .init(cpu->numThreads,enums::Num_OpClass) .flags(Stats::total | Stats::pdf | Stats::dist) ; - statIssuedInstType.ysubnames(Enums::OpClassStrings); + statIssuedInstType.ysubnames(enums::OpClassStrings); // // How long did instructions for a particular FU type wait prior to issue @@ -304,7 +304,7 @@ InstructionQueue::IQStats::IQStats(CPU *cpu, const unsigned &total_width) .flags(Stats::pdf | Stats::dist) ; for (int i=0; i < Num_OpClasses; ++i) { - statFuBusy.subname(i, Enums::OpClassStrings[i]); + statFuBusy.subname(i, enums::OpClassStrings[i]); } fuBusy diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc index 593e5abb06..06a135562f 100644 --- a/src/cpu/o3/regfile.cc +++ b/src/cpu/o3/regfile.cc @@ -162,7 +162,7 @@ PhysRegFile::initFreeList(UnifiedFreeList *freeList) /* depending on the mode we add the vector registers as whole units or * as different elements. */ - if (vecMode == Enums::Full) + if (vecMode == enums::Full) freeList->addRegs(vecRegIds.begin(), vecRegIds.end()); else freeList->addRegs(vecElemIds.begin(), vecElemIds.end()); diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 3447b36dae..a2fbe6722f 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -65,7 +65,7 @@ class PhysRegFile private: using PhysIds = std::vector; - using VecMode = Enums::VecRegRenameMode; + using VecMode = enums::VecRegRenameMode; public: using IdRange = std::pair; diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc index e2f5657a58..071b69c67b 100644 --- a/src/cpu/o3/rename_map.cc +++ b/src/cpu/o3/rename_map.cc @@ -125,7 +125,7 @@ UnifiedRenameMap::init(const BaseISA::RegClasses ®Classes, void UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList) { - if (vecMode == Enums::Elem) { + if (vecMode == enums::Elem) { /* The free list should currently be tracking full registers. */ panic_if(freeList->hasFreeVecElems(), @@ -141,7 +141,7 @@ UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList) freeList->addRegs(range.first, range.second); } - } else if (vecMode == Enums::Full) { + } else if (vecMode == enums::Full) { /* The free list should currently be tracking register elems. */ panic_if(freeList->hasFreeVecRegs(), @@ -162,10 +162,10 @@ UnifiedRenameMap::switchFreeList(UnifiedFreeList* freeList) void UnifiedRenameMap::switchMode(VecMode newVecMode) { - if (newVecMode == Enums::Elem && vecMode == Enums::Full) { + if (newVecMode == enums::Elem && vecMode == enums::Full) { /* Switch to vector element rename mode. */ - vecMode = Enums::Elem; + vecMode = enums::Elem; /* Split the mapping of each arch reg. */ int vec_idx = 0; @@ -180,10 +180,10 @@ UnifiedRenameMap::switchMode(VecMode newVecMode) vec_idx++; } - } else if (newVecMode == Enums::Full && vecMode == Enums::Elem) { + } else if (newVecMode == enums::Full && vecMode == enums::Elem) { /* Switch to full vector register rename mode. */ - vecMode = Enums::Full; + vecMode = enums::Full; /* To rebuild the arch regs we take the easy road: * 1.- Stitch the elems together into vectors. diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh index 8f7e589c28..503f4abac2 100644 --- a/src/cpu/o3/rename_map.hh +++ b/src/cpu/o3/rename_map.hh @@ -189,7 +189,7 @@ class UnifiedRenameMap /** The predicate register rename map */ SimpleRenameMap predMap; - using VecMode = Enums::VecRegRenameMode; + using VecMode = enums::VecRegRenameMode; VecMode vecMode; /** @@ -228,10 +228,10 @@ class UnifiedRenameMap case FloatRegClass: return floatMap.rename(arch_reg); case VecRegClass: - assert(vecMode == Enums::Full); + assert(vecMode == enums::Full); return vecMap.rename(arch_reg); case VecElemClass: - assert(vecMode == Enums::Elem); + assert(vecMode == enums::Elem); return vecElemMap.rename(arch_reg); case VecPredRegClass: return predMap.rename(arch_reg); @@ -270,11 +270,11 @@ class UnifiedRenameMap return floatMap.lookup(arch_reg); case VecRegClass: - assert(vecMode == Enums::Full); + assert(vecMode == enums::Full); return vecMap.lookup(arch_reg); case VecElemClass: - assert(vecMode == Enums::Elem); + assert(vecMode == enums::Elem); return vecElemMap.lookup(arch_reg); case VecPredRegClass: @@ -314,11 +314,11 @@ class UnifiedRenameMap return floatMap.setEntry(arch_reg, phys_reg); case VecRegClass: - assert(vecMode == Enums::Full); + assert(vecMode == enums::Full); return vecMap.setEntry(arch_reg, phys_reg); case VecElemClass: - assert(vecMode == Enums::Elem); + assert(vecMode == enums::Elem); return vecElemMap.setEntry(arch_reg, phys_reg); case VecPredRegClass: @@ -352,7 +352,7 @@ class UnifiedRenameMap { return std::min({intMap.numFreeEntries(), floatMap.numFreeEntries(), - vecMode == Enums::Full ? vecMap.numFreeEntries() : + vecMode == enums::Full ? vecMap.numFreeEntries() : vecElemMap.numFreeEntries(), predMap.numFreeEntries()}); } @@ -362,7 +362,7 @@ class UnifiedRenameMap unsigned numFreeVecEntries() const { - return vecMode == Enums::Full + return vecMode == enums::Full ? vecMap.numFreeEntries() : vecElemMap.numFreeEntries(); } diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh index 104124734b..78c8da276a 100644 --- a/src/cpu/op_class.hh +++ b/src/cpu/op_class.hh @@ -47,61 +47,61 @@ * Do a bunch of wonky stuff to maintain backward compatability so I * don't have to change code in a zillion places. */ -using Enums::OpClass; -using Enums::No_OpClass; +using enums::OpClass; +using enums::No_OpClass; -static const OpClass IntAluOp = Enums::IntAlu; -static const OpClass IntMultOp = Enums::IntMult; -static const OpClass IntDivOp = Enums::IntDiv; -static const OpClass FloatAddOp = Enums::FloatAdd; -static const OpClass FloatCmpOp = Enums::FloatCmp; -static const OpClass FloatCvtOp = Enums::FloatCvt; -static const OpClass FloatMultOp = Enums::FloatMult; -static const OpClass FloatMultAccOp = Enums::FloatMultAcc; -static const OpClass FloatDivOp = Enums::FloatDiv; -static const OpClass FloatMiscOp = Enums::FloatMisc; -static const OpClass FloatSqrtOp = Enums::FloatSqrt; -static const OpClass SimdAddOp = Enums::SimdAdd; -static const OpClass SimdAddAccOp = Enums::SimdAddAcc; -static const OpClass SimdAluOp = Enums::SimdAlu; -static const OpClass SimdCmpOp = Enums::SimdCmp; -static const OpClass SimdCvtOp = Enums::SimdCvt; -static const OpClass SimdMiscOp = Enums::SimdMisc; -static const OpClass SimdMultOp = Enums::SimdMult; -static const OpClass SimdMultAccOp = Enums::SimdMultAcc; -static const OpClass SimdShiftOp = Enums::SimdShift; -static const OpClass SimdShiftAccOp = Enums::SimdShiftAcc; -static const OpClass SimdDivOp = Enums::SimdDiv; -static const OpClass SimdSqrtOp = Enums::SimdSqrt; -static const OpClass SimdReduceAddOp = Enums::SimdReduceAdd; -static const OpClass SimdReduceAluOp = Enums::SimdReduceAlu; -static const OpClass SimdReduceCmpOp = Enums::SimdReduceCmp; -static const OpClass SimdFloatAddOp = Enums::SimdFloatAdd; -static const OpClass SimdFloatAluOp = Enums::SimdFloatAlu; -static const OpClass SimdFloatCmpOp = Enums::SimdFloatCmp; -static const OpClass SimdFloatCvtOp = Enums::SimdFloatCvt; -static const OpClass SimdFloatDivOp = Enums::SimdFloatDiv; -static const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc; -static const OpClass SimdFloatMultOp = Enums::SimdFloatMult; -static const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc; -static const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt; -static const OpClass SimdFloatReduceCmpOp = Enums::SimdFloatReduceCmp; -static const OpClass SimdFloatReduceAddOp = Enums::SimdFloatReduceAdd; -static const OpClass SimdAesOp = Enums::SimdAes; -static const OpClass SimdAesMixOp = Enums::SimdAesMix; -static const OpClass SimdSha1HashOp = Enums::SimdSha1Hash; -static const OpClass SimdSha1Hash2Op = Enums::SimdSha1Hash2; -static const OpClass SimdSha256HashOp = Enums::SimdSha256Hash; -static const OpClass SimdSha256Hash2Op = Enums::SimdSha256Hash2; -static const OpClass SimdShaSigma2Op = Enums::SimdShaSigma2; -static const OpClass SimdShaSigma3Op = Enums::SimdShaSigma3; -static const OpClass SimdPredAluOp = Enums::SimdPredAlu; -static const OpClass MemReadOp = Enums::MemRead; -static const OpClass MemWriteOp = Enums::MemWrite; -static const OpClass FloatMemReadOp = Enums::FloatMemRead; -static const OpClass FloatMemWriteOp = Enums::FloatMemWrite; -static const OpClass IprAccessOp = Enums::IprAccess; -static const OpClass InstPrefetchOp = Enums::InstPrefetch; -static const OpClass Num_OpClasses = Enums::Num_OpClass; +static const OpClass IntAluOp = enums::IntAlu; +static const OpClass IntMultOp = enums::IntMult; +static const OpClass IntDivOp = enums::IntDiv; +static const OpClass FloatAddOp = enums::FloatAdd; +static const OpClass FloatCmpOp = enums::FloatCmp; +static const OpClass FloatCvtOp = enums::FloatCvt; +static const OpClass FloatMultOp = enums::FloatMult; +static const OpClass FloatMultAccOp = enums::FloatMultAcc; +static const OpClass FloatDivOp = enums::FloatDiv; +static const OpClass FloatMiscOp = enums::FloatMisc; +static const OpClass FloatSqrtOp = enums::FloatSqrt; +static const OpClass SimdAddOp = enums::SimdAdd; +static const OpClass SimdAddAccOp = enums::SimdAddAcc; +static const OpClass SimdAluOp = enums::SimdAlu; +static const OpClass SimdCmpOp = enums::SimdCmp; +static const OpClass SimdCvtOp = enums::SimdCvt; +static const OpClass SimdMiscOp = enums::SimdMisc; +static const OpClass SimdMultOp = enums::SimdMult; +static const OpClass SimdMultAccOp = enums::SimdMultAcc; +static const OpClass SimdShiftOp = enums::SimdShift; +static const OpClass SimdShiftAccOp = enums::SimdShiftAcc; +static const OpClass SimdDivOp = enums::SimdDiv; +static const OpClass SimdSqrtOp = enums::SimdSqrt; +static const OpClass SimdReduceAddOp = enums::SimdReduceAdd; +static const OpClass SimdReduceAluOp = enums::SimdReduceAlu; +static const OpClass SimdReduceCmpOp = enums::SimdReduceCmp; +static const OpClass SimdFloatAddOp = enums::SimdFloatAdd; +static const OpClass SimdFloatAluOp = enums::SimdFloatAlu; +static const OpClass SimdFloatCmpOp = enums::SimdFloatCmp; +static const OpClass SimdFloatCvtOp = enums::SimdFloatCvt; +static const OpClass SimdFloatDivOp = enums::SimdFloatDiv; +static const OpClass SimdFloatMiscOp = enums::SimdFloatMisc; +static const OpClass SimdFloatMultOp = enums::SimdFloatMult; +static const OpClass SimdFloatMultAccOp = enums::SimdFloatMultAcc; +static const OpClass SimdFloatSqrtOp = enums::SimdFloatSqrt; +static const OpClass SimdFloatReduceCmpOp = enums::SimdFloatReduceCmp; +static const OpClass SimdFloatReduceAddOp = enums::SimdFloatReduceAdd; +static const OpClass SimdAesOp = enums::SimdAes; +static const OpClass SimdAesMixOp = enums::SimdAesMix; +static const OpClass SimdSha1HashOp = enums::SimdSha1Hash; +static const OpClass SimdSha1Hash2Op = enums::SimdSha1Hash2; +static const OpClass SimdSha256HashOp = enums::SimdSha256Hash; +static const OpClass SimdSha256Hash2Op = enums::SimdSha256Hash2; +static const OpClass SimdShaSigma2Op = enums::SimdShaSigma2; +static const OpClass SimdShaSigma3Op = enums::SimdShaSigma3; +static const OpClass SimdPredAluOp = enums::SimdPredAlu; +static const OpClass MemReadOp = enums::MemRead; +static const OpClass MemWriteOp = enums::MemWrite; +static const OpClass FloatMemReadOp = enums::FloatMemRead; +static const OpClass FloatMemWriteOp = enums::FloatMemWrite; +static const OpClass IprAccessOp = enums::IprAccess; +static const OpClass InstPrefetchOp = enums::InstPrefetch; +static const OpClass Num_OpClasses = enums::Num_OpClass; #endif // __CPU__OP_CLASS_HH__ diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 21b85715c3..1aac862765 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -165,11 +165,11 @@ class SimpleExecContext : public ExecContext .prereq(dcacheStallCycles); statExecutedInstType - .init(Enums::Num_OpClass) + .init(enums::Num_OpClass) .flags(Stats::total | Stats::pdf | Stats::dist); for (unsigned i = 0; i < Num_OpClasses; ++i) { - statExecutedInstType.subname(i, Enums::OpClassStrings[i]); + statExecutedInstType.subname(i, enums::OpClassStrings[i]); } idleFraction = Stats::constant(1.0) - notIdleFraction; diff --git a/src/cpu/testers/traffic_gen/base.cc b/src/cpu/testers/traffic_gen/base.cc index 0dd61998f3..141152283a 100644 --- a/src/cpu/testers/traffic_gen/base.cc +++ b/src/cpu/testers/traffic_gen/base.cc @@ -414,7 +414,7 @@ BaseTrafficGen::createDram(Tick duration, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks, unsigned int nbr_of_banks_util, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks) { return std::shared_ptr(new DramGen(*this, requestorId, @@ -439,7 +439,7 @@ BaseTrafficGen::createDramRot(Tick duration, unsigned int page_size, unsigned int nbr_of_banks, unsigned int nbr_of_banks_util, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks, unsigned int max_seq_count_per_rank) { @@ -473,7 +473,7 @@ BaseTrafficGen::createHybrid(Tick duration, unsigned int buffer_size_nvm, unsigned int nbr_of_banks_nvm, unsigned int nbr_of_banks_util_nvm, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks_dram, unsigned int nbr_of_ranks_nvm, uint8_t nvm_percent) @@ -508,7 +508,7 @@ BaseTrafficGen::createNvm(Tick duration, unsigned int num_seq_pkts, unsigned int buffer_size, unsigned int nbr_of_banks, unsigned int nbr_of_banks_util, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks) { return std::shared_ptr(new NvmGen(*this, requestorId, diff --git a/src/cpu/testers/traffic_gen/base.hh b/src/cpu/testers/traffic_gen/base.hh index 3b7f9680b4..29001c9e33 100644 --- a/src/cpu/testers/traffic_gen/base.hh +++ b/src/cpu/testers/traffic_gen/base.hh @@ -276,7 +276,7 @@ class BaseTrafficGen : public ClockedObject uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks, unsigned int nbr_of_banks_util, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks); std::shared_ptr createDramRot( @@ -286,7 +286,7 @@ class BaseTrafficGen : public ClockedObject uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks, unsigned int nbr_of_banks_util, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks, unsigned int max_seq_count_per_rank); @@ -300,7 +300,7 @@ class BaseTrafficGen : public ClockedObject unsigned int nbr_of_banks_dram, unsigned int nbr_of_banks_util_dram, unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm, unsigned int nbr_of_banks_nvm, unsigned int nbr_of_banks_util_nvm, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks_dram, unsigned int nbr_of_ranks_nvm, uint8_t nvm_percent); @@ -312,7 +312,7 @@ class BaseTrafficGen : public ClockedObject uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int buffer_size, unsigned int nbr_of_banks, unsigned int nbr_of_banks_util, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks); std::shared_ptr createStrided( diff --git a/src/cpu/testers/traffic_gen/dram_gen.cc b/src/cpu/testers/traffic_gen/dram_gen.cc index e29f6d1475..be29b5dfa4 100644 --- a/src/cpu/testers/traffic_gen/dram_gen.cc +++ b/src/cpu/testers/traffic_gen/dram_gen.cc @@ -53,7 +53,7 @@ DramGen::DramGen(SimObject &obj, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks) : RandomGen(obj, requestor_id, _duration, start_addr, end_addr, _blocksize, cacheline_size, min_period, max_period, @@ -105,13 +105,13 @@ DramGen::getNextPacket() } else { // increment the column by one - if (addrMapping == Enums::RoRaBaCoCh || - addrMapping == Enums::RoRaBaChCo) + if (addrMapping == enums::RoRaBaCoCh || + addrMapping == enums::RoRaBaChCo) // Simply increment addr by blocksize to increment // the column by one addr += blocksize; - else if (addrMapping == Enums::RoCoRaBaCh) { + else if (addrMapping == enums::RoCoRaBaCh) { // Explicity increment the column bits unsigned int new_col = ((addr / blocksize / nbrOfBanksDRAM / nbrOfRanks) % @@ -166,8 +166,8 @@ DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank) unsigned int new_col = random_mt.random(0, columns_per_page - numSeqPkts); - if (addrMapping == Enums::RoRaBaCoCh || - addrMapping == Enums::RoRaBaChCo) { + if (addrMapping == enums::RoRaBaCoCh || + addrMapping == enums::RoRaBaChCo) { // Block bits, then page bits, then bank bits, then rank bits replaceBits(addr, blockBits + pageBits + bankBits - 1, blockBits + pageBits, new_bank); @@ -176,7 +176,7 @@ DramGen::genStartAddr(unsigned int new_bank, unsigned int new_rank) replaceBits(addr, blockBits + pageBits + bankBits +rankBits - 1, blockBits + pageBits + bankBits, new_rank); } - } else if (addrMapping == Enums::RoCoRaBaCh) { + } else if (addrMapping == enums::RoCoRaBaCh) { // Block bits, then bank bits, then rank bits, then page bits replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank); replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1, diff --git a/src/cpu/testers/traffic_gen/dram_gen.hh b/src/cpu/testers/traffic_gen/dram_gen.hh index b09081bd2c..6b398022c6 100644 --- a/src/cpu/testers/traffic_gen/dram_gen.hh +++ b/src/cpu/testers/traffic_gen/dram_gen.hh @@ -90,7 +90,7 @@ class DramGen : public RandomGen uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks); PacketPtr getNextPacket(); @@ -136,7 +136,7 @@ class DramGen : public RandomGen const unsigned int nbrOfBanksUtil; /** Address mapping to be used */ - Enums::AddrMap addrMapping; + enums::AddrMap addrMapping; /** Number of rank bits in DRAM address*/ const unsigned int rankBits; diff --git a/src/cpu/testers/traffic_gen/dram_rot_gen.cc b/src/cpu/testers/traffic_gen/dram_rot_gen.cc index 7dad914d68..accbaf0458 100644 --- a/src/cpu/testers/traffic_gen/dram_rot_gen.cc +++ b/src/cpu/testers/traffic_gen/dram_rot_gen.cc @@ -98,13 +98,13 @@ DramRotGen::getNextPacket() } else { // increment the column by one - if (addrMapping == Enums::RoRaBaCoCh || - addrMapping == Enums::RoRaBaChCo) + if (addrMapping == enums::RoRaBaCoCh || + addrMapping == enums::RoRaBaChCo) // Simply increment addr by blocksize to // increment the column by one addr += blocksize; - else if (addrMapping == Enums::RoCoRaBaCh) { + else if (addrMapping == enums::RoCoRaBaCh) { // Explicity increment the column bits unsigned int new_col = ((addr / blocksize / diff --git a/src/cpu/testers/traffic_gen/dram_rot_gen.hh b/src/cpu/testers/traffic_gen/dram_rot_gen.hh index 34140ac88e..7365a973ea 100644 --- a/src/cpu/testers/traffic_gen/dram_rot_gen.hh +++ b/src/cpu/testers/traffic_gen/dram_rot_gen.hh @@ -89,7 +89,7 @@ class DramRotGen : public DramGen uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks, unsigned int max_seq_count_per_rank) : DramGen(obj, requestor_id, _duration, start_addr, end_addr, diff --git a/src/cpu/testers/traffic_gen/hybrid_gen.cc b/src/cpu/testers/traffic_gen/hybrid_gen.cc index 979eda89ab..5dc92e8a58 100644 --- a/src/cpu/testers/traffic_gen/hybrid_gen.cc +++ b/src/cpu/testers/traffic_gen/hybrid_gen.cc @@ -59,7 +59,7 @@ HybridGen::HybridGen(SimObject &obj, unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm, unsigned int nbr_of_banks_nvm, unsigned int nbr_of_banks_util_nvm, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks_dram, unsigned int nbr_of_ranks_nvm, uint8_t nvm_percent) @@ -197,13 +197,13 @@ HybridGen::getNextPacket() } else { // increment the column by one - if (addrMapping == Enums::RoRaBaCoCh || - addrMapping == Enums::RoRaBaChCo) + if (addrMapping == enums::RoRaBaCoCh || + addrMapping == enums::RoRaBaChCo) // Simply increment addr by blocksize to increment // the column by one addr += blocksize; - else if (addrMapping == Enums::RoCoRaBaCh) { + else if (addrMapping == enums::RoCoRaBaCh) { // Explicity increment the column bits unsigned int new_col = ((addr / blocksize / nbrOfBanks / nbrOfRanks) % @@ -258,8 +258,8 @@ HybridGen::genStartAddr(unsigned int new_bank, unsigned int new_rank) unsigned int new_col = random_mt.random(0, burst_per_page - numSeqPkts); - if (addrMapping == Enums::RoRaBaCoCh || - addrMapping == Enums::RoRaBaChCo) { + if (addrMapping == enums::RoRaBaCoCh || + addrMapping == enums::RoRaBaChCo) { // Block bits, then page bits, then bank bits, then rank bits replaceBits(addr, blockBits + pageBits + bankBits - 1, blockBits + pageBits, new_bank); @@ -268,7 +268,7 @@ HybridGen::genStartAddr(unsigned int new_bank, unsigned int new_rank) replaceBits(addr, blockBits + pageBits + bankBits +rankBits - 1, blockBits + pageBits + bankBits, new_rank); } - } else if (addrMapping == Enums::RoCoRaBaCh) { + } else if (addrMapping == enums::RoCoRaBaCh) { // Block bits, then bank bits, then rank bits, then page bits replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank); replaceBits(addr, blockBits + bankBits + rankBits + pageBits - 1, diff --git a/src/cpu/testers/traffic_gen/hybrid_gen.hh b/src/cpu/testers/traffic_gen/hybrid_gen.hh index e500465d99..f0d158e684 100644 --- a/src/cpu/testers/traffic_gen/hybrid_gen.hh +++ b/src/cpu/testers/traffic_gen/hybrid_gen.hh @@ -106,7 +106,7 @@ class HybridGen : public BaseGen unsigned int nbr_of_banks_dram, unsigned int nbr_of_banks_util_dram, unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm, unsigned int nbr_of_banks_nvm, unsigned int nbr_of_banks_util_nvm, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks_dram, unsigned int nbr_of_ranks_nvm, uint8_t nvm_percent); @@ -204,7 +204,7 @@ class HybridGen : public BaseGen const unsigned int nbrOfBanksUtilNvm; /** Address mapping to be used */ - Enums::AddrMap addrMapping; + enums::AddrMap addrMapping; /** Number of ranks to be utilized for a given configuration */ const unsigned int nbrOfRanksDram; diff --git a/src/cpu/testers/traffic_gen/nvm_gen.cc b/src/cpu/testers/traffic_gen/nvm_gen.cc index b43b9f9705..ffd262d235 100644 --- a/src/cpu/testers/traffic_gen/nvm_gen.cc +++ b/src/cpu/testers/traffic_gen/nvm_gen.cc @@ -53,7 +53,7 @@ NvmGen::NvmGen(SimObject &obj, unsigned int num_seq_pkts, unsigned int buffer_size, unsigned int nbr_of_banks, unsigned int nbr_of_banks_util, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks) : RandomGen(obj, requestor_id, _duration, start_addr, end_addr, _blocksize, cacheline_size, min_period, max_period, @@ -105,13 +105,13 @@ NvmGen::getNextPacket() } else { // increment the column by one - if (addrMapping == Enums::RoRaBaCoCh || - addrMapping == Enums::RoRaBaChCo) + if (addrMapping == enums::RoRaBaCoCh || + addrMapping == enums::RoRaBaChCo) // Simply increment addr by blocksize to increment // the column by one addr += blocksize; - else if (addrMapping == Enums::RoCoRaBaCh) { + else if (addrMapping == enums::RoCoRaBaCh) { // Explicity increment the column bits unsigned int new_col = ((addr / blocksize / nbrOfBanksNVM / nbrOfRanks) % @@ -161,8 +161,8 @@ NvmGen::genStartAddr(unsigned int new_bank, unsigned int new_rank) unsigned int new_col = random_mt.random(0, burst_per_buffer - numSeqPkts); - if (addrMapping == Enums::RoRaBaCoCh || - addrMapping == Enums::RoRaBaChCo) { + if (addrMapping == enums::RoRaBaCoCh || + addrMapping == enums::RoRaBaChCo) { // Block bits, then buffer bits, then bank bits, then rank bits replaceBits(addr, blockBits + bufferBits + bankBits - 1, blockBits + bufferBits, new_bank); @@ -172,7 +172,7 @@ NvmGen::genStartAddr(unsigned int new_bank, unsigned int new_rank) rankBits - 1, blockBits + bufferBits + bankBits, new_rank); } - } else if (addrMapping == Enums::RoCoRaBaCh) { + } else if (addrMapping == enums::RoCoRaBaCh) { // Block bits, then bank bits, then rank bits, then buffer bits replaceBits(addr, blockBits + bankBits - 1, blockBits, new_bank); replaceBits(addr, blockBits + bankBits + rankBits + bufferBits - 1, diff --git a/src/cpu/testers/traffic_gen/nvm_gen.hh b/src/cpu/testers/traffic_gen/nvm_gen.hh index 7bc90c5985..d72353d36b 100644 --- a/src/cpu/testers/traffic_gen/nvm_gen.hh +++ b/src/cpu/testers/traffic_gen/nvm_gen.hh @@ -90,7 +90,7 @@ class NvmGen : public RandomGen uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int buffer_size, unsigned int nbr_of_banks, unsigned int nbr_of_banks_util, - Enums::AddrMap addr_mapping, + enums::AddrMap addr_mapping, unsigned int nbr_of_ranks); PacketPtr getNextPacket(); @@ -136,7 +136,7 @@ class NvmGen : public RandomGen const unsigned int nbrOfBanksUtil; /** Address mapping to be used */ - Enums::AddrMap addrMapping; + enums::AddrMap addrMapping; /** Number of rank bits in NVM address*/ const unsigned int rankBits; diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc b/src/cpu/testers/traffic_gen/traffic_gen.cc index 6e1a00a304..ffae679168 100644 --- a/src/cpu/testers/traffic_gen/traffic_gen.cc +++ b/src/cpu/testers/traffic_gen/traffic_gen.cc @@ -220,8 +220,8 @@ TrafficGen::parseConfig() is >> stride_size >> page_size >> nbr_of_banks >> nbr_of_banks_util >> _addr_mapping >> nbr_of_ranks; - Enums::AddrMap addr_mapping = - static_cast(_addr_mapping); + enums::AddrMap addr_mapping = + static_cast(_addr_mapping); if (stride_size > page_size) warn("Memory generator stride size (%d) is greater" diff --git a/src/cpu/timing_expr.cc b/src/cpu/timing_expr.cc index 5a13b1b0ff..2e361cfa3b 100644 --- a/src/cpu/timing_expr.cc +++ b/src/cpu/timing_expr.cc @@ -90,23 +90,23 @@ uint64_t TimingExprUn::eval(TimingExprEvalContext &context) uint64_t ret = 0; switch (op) { - case Enums::timingExprSizeInBits: + case enums::timingExprSizeInBits: if (arg_value == 0) ret = 0; else ret = ceilLog2(arg_value); break; - case Enums::timingExprNot: + case enums::timingExprNot: ret = arg_value != 0; break; - case Enums::timingExprInvert: + case enums::timingExprInvert: ret = ~arg_value; break; - case Enums::timingExprSignExtend32To64: + case enums::timingExprSignExtend32To64: ret = static_cast( static_cast(arg_value)); break; - case Enums::timingExprAbs: + case enums::timingExprAbs: if (static_cast(arg_value) < 0) ret = -arg_value; else @@ -126,59 +126,59 @@ uint64_t TimingExprBin::eval(TimingExprEvalContext &context) uint64_t ret = 0; switch (op) { - case Enums::timingExprAdd: + case enums::timingExprAdd: ret = left_value + right_value; break; - case Enums::timingExprSub: + case enums::timingExprSub: ret = left_value - right_value; break; - case Enums::timingExprUMul: + case enums::timingExprUMul: ret = left_value * right_value; break; - case Enums::timingExprUDiv: + case enums::timingExprUDiv: if (right_value != 0) { ret = left_value / right_value; } break; - case Enums::timingExprUCeilDiv: + case enums::timingExprUCeilDiv: if (right_value != 0) { ret = (left_value + (right_value - 1)) / right_value; } break; - case Enums::timingExprSMul: + case enums::timingExprSMul: ret = static_cast(left_value) * static_cast(right_value); break; - case Enums::timingExprSDiv: + case enums::timingExprSDiv: if (right_value != 0) { ret = static_cast(left_value) / static_cast(right_value); } break; - case Enums::timingExprEqual: + case enums::timingExprEqual: ret = left_value == right_value; break; - case Enums::timingExprNotEqual: + case enums::timingExprNotEqual: ret = left_value != right_value; break; - case Enums::timingExprULessThan: + case enums::timingExprULessThan: ret = left_value < right_value; break; - case Enums::timingExprUGreaterThan: + case enums::timingExprUGreaterThan: ret = left_value > right_value; break; - case Enums::timingExprSLessThan: + case enums::timingExprSLessThan: ret = static_cast(left_value) < static_cast(right_value); break; - case Enums::timingExprSGreaterThan: + case enums::timingExprSGreaterThan: ret = static_cast(left_value) > static_cast(right_value); break; - case Enums::timingExprAnd: + case enums::timingExprAnd: ret = (left_value != 0) && (right_value != 0); break; - case Enums::timingExprOr: + case enums::timingExprOr: ret = (left_value != 0) || (right_value != 0); break; default: diff --git a/src/cpu/timing_expr.hh b/src/cpu/timing_expr.hh index 35e1643491..f2163156b2 100644 --- a/src/cpu/timing_expr.hh +++ b/src/cpu/timing_expr.hh @@ -165,7 +165,7 @@ class TimingExprRef : public TimingExpr class TimingExprUn : public TimingExpr { public: - Enums::TimingExprOp op; + enums::TimingExprOp op; TimingExpr *arg; TimingExprUn(const TimingExprUnParams ¶ms) : @@ -180,7 +180,7 @@ class TimingExprUn : public TimingExpr class TimingExprBin : public TimingExpr { public: - Enums::TimingExprOp op; + enums::TimingExprOp op; TimingExpr *left; TimingExpr *right; diff --git a/src/dev/arm/flash_device.cc b/src/dev/arm/flash_device.cc index a8a732a649..f3277d518f 100644 --- a/src/dev/arm/flash_device.cc +++ b/src/dev/arm/flash_device.cc @@ -128,7 +128,7 @@ FlashDevice::initializeFlash(uint64_t disk_size, uint32_t sector_size) for (uint32_t count = 0; count < pagesPerDisk; count++) { //setup lookup table + physical aspects - if (dataDistribution == Enums::stripe) { + if (dataDistribution == enums::stripe) { locationTable[count].page = count / blocksPerDisk; locationTable[count].block = count % blocksPerDisk; diff --git a/src/dev/arm/flash_device.hh b/src/dev/arm/flash_device.hh index 4696c099e9..7225f7491f 100644 --- a/src/dev/arm/flash_device.hh +++ b/src/dev/arm/flash_device.hh @@ -167,7 +167,7 @@ class FlashDevice : public AbstractNVM const Tick eraseLatency; /** Flash organization */ - const Enums::DataDistribution dataDistribution; + const enums::DataDistribution dataDistribution; const uint32_t numPlanes; /** RequestHandler stats */ diff --git a/src/dev/arm/fvp_base_pwr_ctrl.cc b/src/dev/arm/fvp_base_pwr_ctrl.cc index beeb92642d..781e4757ca 100644 --- a/src/dev/arm/fvp_base_pwr_ctrl.cc +++ b/src/dev/arm/fvp_base_pwr_ctrl.cc @@ -280,7 +280,7 @@ FVPBasePwrCtrl::powerCoreOn(ThreadContext *const tc, PwrStatus *const pwrs) npwrs->pc = 0; } } - tc->getCpuPtr()->powerState->set(Enums::PwrState::ON); + tc->getCpuPtr()->powerState->set(enums::PwrState::ON); } void @@ -295,7 +295,7 @@ FVPBasePwrCtrl::powerCoreOff(ThreadContext *const tc, PwrStatus *const pwrs) pwrs->pc = 0; // Clear power-on reason pwrs->wk = 0; - tc->getCpuPtr()->powerState->set(Enums::PwrState::OFF); + tc->getCpuPtr()->powerState->set(enums::PwrState::OFF); } void diff --git a/src/dev/arm/gpu_nomali.cc b/src/dev/arm/gpu_nomali.cc index 989852a939..809ef59ba8 100644 --- a/src/dev/arm/gpu_nomali.cc +++ b/src/dev/arm/gpu_nomali.cc @@ -46,10 +46,10 @@ #include "params/CustomNoMaliGpu.hh" #include "params/NoMaliGpu.hh" -static const std::map gpuTypeMap{ - { Enums::T60x, NOMALI_GPU_T60X }, - { Enums::T62x, NOMALI_GPU_T62X }, - { Enums::T760, NOMALI_GPU_T760 }, +static const std::map gpuTypeMap{ + { enums::T60x, NOMALI_GPU_T60X }, + { enums::T62x, NOMALI_GPU_T62X }, + { enums::T760, NOMALI_GPU_T760 }, }; NoMaliGpu::NoMaliGpu(const NoMaliGpuParams &p) @@ -72,7 +72,7 @@ NoMaliGpu::NoMaliGpu(const NoMaliGpuParams &p) const auto it_gpu(gpuTypeMap.find(p.gpu_type)); if (it_gpu == gpuTypeMap.end()) { fatal("Unrecognized GPU type: %s (%i)\n", - Enums::NoMaliGpuTypeStrings[p.gpu_type], p.gpu_type); + enums::NoMaliGpuTypeStrings[p.gpu_type], p.gpu_type); } cfg.type = it_gpu->second; diff --git a/src/dev/arm/hdlcd.hh b/src/dev/arm/hdlcd.hh index 4f75df4359..457265bd56 100644 --- a/src/dev/arm/hdlcd.hh +++ b/src/dev/arm/hdlcd.hh @@ -370,7 +370,7 @@ class HDLcd: public AmbaDmaDevice std::unique_ptr imgWriter; /** Image Format */ - Enums::ImageFormat imgFormat; + enums::ImageFormat imgFormat; /** Picture of what the current frame buffer looks like */ OutputStream *pic = nullptr; diff --git a/src/dev/arm/pci_host.cc b/src/dev/arm/pci_host.cc index ff7a21c059..c50a3027f7 100644 --- a/src/dev/arm/pci_host.cc +++ b/src/dev/arm/pci_host.cc @@ -55,13 +55,13 @@ GenericArmPciHost::mapPciInterrupt(const PciBusAddr &addr, PciIntPin pin) const addr.bus, addr.dev, addr.func); switch (intPolicy) { - case Enums::ARM_PCI_INT_STATIC: + case enums::ARM_PCI_INT_STATIC: return GenericPciHost::mapPciInterrupt(addr, pin); - case Enums::ARM_PCI_INT_DEV: + case enums::ARM_PCI_INT_DEV: return intBase + (addr.dev % intCount); - case Enums::ARM_PCI_INT_PIN: + case enums::ARM_PCI_INT_PIN: return intBase + ((static_cast(pin) - 1) % intCount); default: diff --git a/src/dev/arm/pci_host.hh b/src/dev/arm/pci_host.hh index bf48b3d879..c6cb2b566e 100644 --- a/src/dev/arm/pci_host.hh +++ b/src/dev/arm/pci_host.hh @@ -56,7 +56,7 @@ class GenericArmPciHost PciIntPin pin) const override; protected: - const Enums::ArmPciIntRouting intPolicy; + const enums::ArmPciIntRouting intPolicy; const uint32_t intBase; const uint32_t intCount; }; diff --git a/src/dev/x86/i8259.cc b/src/dev/x86/i8259.cc index c2817b9bab..70d5cc2f8e 100644 --- a/src/dev/x86/i8259.cc +++ b/src/dev/x86/i8259.cc @@ -190,7 +190,7 @@ X86ISA::I8259::write(PacketPtr pkt) break; case 0x2: DPRINTF(I8259, "Received initialization command word 3.\n"); - if (mode == Enums::I8259Master) { + if (mode == enums::I8259Master) { DPRINTF(I8259, "Responders attached to " "IRQs:%s%s%s%s%s%s%s%s\n", bits(val, 0) ? " 0" : "", diff --git a/src/dev/x86/i8259.hh b/src/dev/x86/i8259.hh index 8b024ba2d3..c876eb1879 100644 --- a/src/dev/x86/i8259.hh +++ b/src/dev/x86/i8259.hh @@ -48,7 +48,7 @@ class I8259 : public BasicPioDevice Tick latency; std::vector *> output; std::vector *> inputs; - Enums::X86I8259CascadeMode mode; + enums::X86I8259CascadeMode mode; I8259 *slave; // Interrupt Request Register diff --git a/src/gpu-compute/compute_unit.cc b/src/gpu-compute/compute_unit.cc index b845151dbe..d48917d769 100644 --- a/src/gpu-compute/compute_unit.cc +++ b/src/gpu-compute/compute_unit.cc @@ -1230,7 +1230,7 @@ ComputeUnit::injectGlobalMemFence(GPUDynInstPtr gpuDynInst, RequestPtr req) { assert(gpuDynInst->isGlobalSeg() || - gpuDynInst->executedAs() == Enums::SC_GLOBAL); + gpuDynInst->executedAs() == enums::SC_GLOBAL); if (!req) { req = std::make_shared( @@ -1452,13 +1452,13 @@ ComputeUnit::DTLBPort::recvTimingResp(PacketPtr pkt) Addr last = 0; switch(computeUnit->prefetchType) { - case Enums::PF_CU: + case enums::PF_CU: last = computeUnit->lastVaddrCU[mp_index]; break; - case Enums::PF_PHASE: + case enums::PF_PHASE: last = computeUnit->lastVaddrSimd[simdId][mp_index]; break; - case Enums::PF_WF: + case enums::PF_WF: last = computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index]; default: break; @@ -1477,7 +1477,7 @@ ComputeUnit::DTLBPort::recvTimingResp(PacketPtr pkt) computeUnit->lastVaddrSimd[simdId][mp_index] = vaddr; computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index] = vaddr; - stride = (computeUnit->prefetchType == Enums::PF_STRIDE) ? + stride = (computeUnit->prefetchType == enums::PF_STRIDE) ? computeUnit->prefetchStride: stride; DPRINTF(GPUPrefetch, "%#x to: CU[%d][%d][%d][%d]\n", vaddr, @@ -1836,28 +1836,28 @@ ComputeUnit::updateInstStats(GPUDynInstPtr gpuDynInst) if (gpuDynInst->isLoad()) { switch (gpuDynInst->executedAs()) { - case Enums::SC_SPILL: + case enums::SC_SPILL: stats.spillReads++; break; - case Enums::SC_GLOBAL: + case enums::SC_GLOBAL: stats.globalReads++; break; - case Enums::SC_GROUP: + case enums::SC_GROUP: stats.groupReads++; break; - case Enums::SC_PRIVATE: + case enums::SC_PRIVATE: stats.privReads++; break; - case Enums::SC_READONLY: + case enums::SC_READONLY: stats.readonlyReads++; break; - case Enums::SC_KERNARG: + case enums::SC_KERNARG: stats.kernargReads++; break; - case Enums::SC_ARG: + case enums::SC_ARG: stats.argReads++; break; - case Enums::SC_NONE: + case enums::SC_NONE: /** * this case can occur for flat mem insts * who execute with EXEC = 0 @@ -1869,28 +1869,28 @@ ComputeUnit::updateInstStats(GPUDynInstPtr gpuDynInst) } } else if (gpuDynInst->isStore()) { switch (gpuDynInst->executedAs()) { - case Enums::SC_SPILL: + case enums::SC_SPILL: stats.spillWrites++; break; - case Enums::SC_GLOBAL: + case enums::SC_GLOBAL: stats.globalWrites++; break; - case Enums::SC_GROUP: + case enums::SC_GROUP: stats.groupWrites++; break; - case Enums::SC_PRIVATE: + case enums::SC_PRIVATE: stats.privWrites++; break; - case Enums::SC_READONLY: + case enums::SC_READONLY: stats.readonlyWrites++; break; - case Enums::SC_KERNARG: + case enums::SC_KERNARG: stats.kernargWrites++; break; - case Enums::SC_ARG: + case enums::SC_ARG: stats.argWrites++; break; - case Enums::SC_NONE: + case enums::SC_NONE: /** * this case can occur for flat mem insts * who execute with EXEC = 0 diff --git a/src/gpu-compute/compute_unit.hh b/src/gpu-compute/compute_unit.hh index cdefb2be14..db4daf22f3 100644 --- a/src/gpu-compute/compute_unit.hh +++ b/src/gpu-compute/compute_unit.hh @@ -334,7 +334,7 @@ class ComputeUnit : public ClockedObject std::vector lastVaddrCU; std::vector> lastVaddrSimd; std::vector>> lastVaddrWF; - Enums::PrefetchType prefetchType; + enums::PrefetchType prefetchType; EXEC_POLICY exec_policy; bool debugSegFault; diff --git a/src/gpu-compute/gpu_dyn_inst.cc b/src/gpu-compute/gpu_dyn_inst.cc index 4bdceccc5a..ea64640704 100644 --- a/src/gpu-compute/gpu_dyn_inst.cc +++ b/src/gpu-compute/gpu_dyn_inst.cc @@ -281,7 +281,7 @@ GPUDynInst::seqNum() const return _seqNum; } -Enums::StorageClassType +enums::StorageClassType GPUDynInst::executedAs() { return _staticInst->executed_as; @@ -741,11 +741,11 @@ GPUDynInst::doApertureCheck(const VectorMask &mask) if (mask[lane]) { if (computeUnit()->shader->isLdsApe(addr[lane])) { // group segment - staticInstruction()->executed_as = Enums::SC_GROUP; + staticInstruction()->executed_as = enums::SC_GROUP; break; } else if (computeUnit()->shader->isScratchApe(addr[lane])) { // private segment - staticInstruction()->executed_as = Enums::SC_PRIVATE; + staticInstruction()->executed_as = enums::SC_PRIVATE; break; } else if (computeUnit()->shader->isGpuVmApe(addr[lane])) { // we won't support GPUVM @@ -757,18 +757,18 @@ GPUDynInst::doApertureCheck(const VectorMask &mask) addr[lane]); } else { // global memory segment - staticInstruction()->executed_as = Enums::SC_GLOBAL; + staticInstruction()->executed_as = enums::SC_GLOBAL; break; } } } // we should have found the segment - assert(executedAs() != Enums::SC_NONE); + assert(executedAs() != enums::SC_NONE); // flat accesses should not straddle multiple APEs so we // must check that all addresses fall within the same APE - if (executedAs() == Enums::SC_GROUP) { + if (executedAs() == enums::SC_GROUP) { for (int lane = 0; lane < computeUnit()->wfSize(); ++lane) { if (mask[lane]) { // if the first valid addr we found above was LDS, @@ -776,7 +776,7 @@ GPUDynInst::doApertureCheck(const VectorMask &mask) assert(computeUnit()->shader->isLdsApe(addr[lane])); } } - } else if (executedAs() == Enums::SC_PRIVATE) { + } else if (executedAs() == enums::SC_PRIVATE) { for (int lane = 0; lane < computeUnit()->wfSize(); ++lane) { if (mask[lane]) { // if the first valid addr we found above was private, @@ -813,7 +813,7 @@ GPUDynInst::resolveFlatSegment(const VectorMask &mask) // 2. Set the execUnitId based an the aperture check. // 3. Decrement any extra resources that were reserved. Other // resources are released as normal, below. - if (executedAs() == Enums::SC_GLOBAL) { + if (executedAs() == enums::SC_GLOBAL) { // no transormation for global segment wavefront()->execUnitId = wavefront()->flatGmUnitId; if (isLoad()) { @@ -826,7 +826,7 @@ GPUDynInst::resolveFlatSegment(const VectorMask &mask) } else { panic("Invalid memory operation!\n"); } - } else if (executedAs() == Enums::SC_GROUP) { + } else if (executedAs() == enums::SC_GROUP) { for (int lane = 0; lane < wavefront()->computeUnit->wfSize(); ++lane) { if (mask[lane]) { // flat address calculation goes here. @@ -846,7 +846,7 @@ GPUDynInst::resolveFlatSegment(const VectorMask &mask) } else { panic("Invalid memory operation!\n"); } - } else if (executedAs() == Enums::SC_PRIVATE) { + } else if (executedAs() == enums::SC_PRIVATE) { /** * Flat instructions may resolve to the private segment (scratch), * which is backed by main memory and provides per-lane scratch diff --git a/src/gpu-compute/gpu_dyn_inst.hh b/src/gpu-compute/gpu_dyn_inst.hh index e67ffe9d25..ab7ccb80dc 100644 --- a/src/gpu-compute/gpu_dyn_inst.hh +++ b/src/gpu-compute/gpu_dyn_inst.hh @@ -159,7 +159,7 @@ class GPUDynInst : public GPUExecContext InstSeqNum seqNum() const; - Enums::StorageClassType executedAs(); + enums::StorageClassType executedAs(); // virtual address for scalar memory operations Addr scalarAddr; diff --git a/src/gpu-compute/gpu_static_inst.cc b/src/gpu-compute/gpu_static_inst.cc index 2344c0a38c..12935b0e60 100644 --- a/src/gpu-compute/gpu_static_inst.cc +++ b/src/gpu-compute/gpu_static_inst.cc @@ -36,7 +36,7 @@ #include "debug/GPUInst.hh" GPUStaticInst::GPUStaticInst(const std::string &opcode) - : executed_as(Enums::SC_NONE), _opcode(opcode), + : executed_as(enums::SC_NONE), _opcode(opcode), _instNum(0), _instAddr(0), srcVecDWords(-1), dstVecDWords(-1), srcScalarDWords(-1), dstScalarDWords(-1), maxOpSize(-1) { diff --git a/src/gpu-compute/gpu_static_inst.hh b/src/gpu-compute/gpu_static_inst.hh index 62db9c4402..ed753c5784 100644 --- a/src/gpu-compute/gpu_static_inst.hh +++ b/src/gpu-compute/gpu_static_inst.hh @@ -237,25 +237,25 @@ class GPUStaticInst : public GPUStaticInstFlags static uint64_t dynamic_id_count; // For flat memory accesses - Enums::StorageClassType executed_as; + enums::StorageClassType executed_as; void setFlag(Flags flag) { _flags[flag] = true; if (isGroupSeg()) { - executed_as = Enums::SC_GROUP; + executed_as = enums::SC_GROUP; } else if (isGlobalSeg()) { - executed_as = Enums::SC_GLOBAL; + executed_as = enums::SC_GLOBAL; } else if (isPrivateSeg()) { - executed_as = Enums::SC_PRIVATE; + executed_as = enums::SC_PRIVATE; } else if (isSpillSeg()) { - executed_as = Enums::SC_SPILL; + executed_as = enums::SC_SPILL; } else if (isReadOnlySeg()) { - executed_as = Enums::SC_READONLY; + executed_as = enums::SC_READONLY; } else if (isKernArgSeg()) { - executed_as = Enums::SC_KERNARG; + executed_as = enums::SC_KERNARG; } else if (isArgSeg()) { - executed_as = Enums::SC_ARG; + executed_as = enums::SC_ARG; } } const std::string& opcode() const { return _opcode; } diff --git a/src/gpu-compute/wavefront.cc b/src/gpu-compute/wavefront.cc index e8bcc14f9c..a933308a1d 100644 --- a/src/gpu-compute/wavefront.cc +++ b/src/gpu-compute/wavefront.cc @@ -565,7 +565,7 @@ bool Wavefront::isGmInstruction(GPUDynInstPtr ii) { if (ii->isGlobalMem() || - (ii->isFlat() && ii->executedAs() == Enums::SC_GLOBAL)) { + (ii->isFlat() && ii->executedAs() == enums::SC_GLOBAL)) { return true; } @@ -576,7 +576,7 @@ bool Wavefront::isLmInstruction(GPUDynInstPtr ii) { if (ii->isLocalMem() || - (ii->isFlat() && ii->executedAs() == Enums::SC_GROUP)) { + (ii->isFlat() && ii->executedAs() == enums::SC_GROUP)) { return true; } @@ -1058,9 +1058,9 @@ Wavefront::exec() bool flat_as_gm = false; bool flat_as_lm = false; if (ii->isFlat()) { - flat_as_gm = (ii->executedAs() == Enums::SC_GLOBAL) || - (ii->executedAs() == Enums::SC_PRIVATE); - flat_as_lm = (ii->executedAs() == Enums::SC_GROUP); + flat_as_gm = (ii->executedAs() == enums::SC_GLOBAL) || + (ii->executedAs() == enums::SC_PRIVATE); + flat_as_lm = (ii->executedAs() == enums::SC_GROUP); } // Single precision ALU or Branch or Return or Special instruction diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 225de58695..fac376e930 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -1401,7 +1401,7 @@ void BaseCache::maintainClusivity(bool from_cache, CacheBlk *blk) { if (from_cache && blk && blk->isValid() && - !blk->isSet(CacheBlk::DirtyBit) && clusivity == Enums::mostly_excl) { + !blk->isSet(CacheBlk::DirtyBit) && clusivity == enums::mostly_excl) { // if we have responded to a cache, and our block is still // valid, but not dirty, and this cache is mostly exclusive // with respect to the cache above, drop the block diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 9b1715ca89..458440d1a1 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -437,7 +437,7 @@ class BaseCache : public ClockedObject */ inline bool allocOnFill(MemCmd cmd) const { - return clusivity == Enums::mostly_incl || + return clusivity == enums::mostly_incl || cmd == MemCmd::WriteLineReq || cmd == MemCmd::ReadReq || cmd == MemCmd::WriteReq || @@ -929,7 +929,7 @@ class BaseCache : public ClockedObject * fill into both this cache and the cache above on a miss. Note * that we currently do not support strict clusivity policies. */ - const Enums::Clusivity clusivity; + const enums::Clusivity clusivity; /** * Is this cache read only, for example the instruction cache, or diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index 900cf48a39..dbebc5558f 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -527,7 +527,7 @@ Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, // * this cache is mostly exclusive and will not fill (since // it does not fill it will have to writeback the dirty data // immediately which generates uneccesary writebacks). - bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl; + bool force_clean_rsp = isReadOnly || clusivity == enums::mostly_excl; cmd = needsWritable ? MemCmd::ReadExReq : (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); } diff --git a/src/mem/mem_ctrl.cc b/src/mem/mem_ctrl.cc index 6f871b1100..a7e7dadd02 100644 --- a/src/mem/mem_ctrl.cc +++ b/src/mem/mem_ctrl.cc @@ -568,7 +568,7 @@ MemCtrl::chooseNext(MemPacketQueue& queue, Tick extra_col_delay) } else { DPRINTF(MemCtrl, "Single request, going to a busy rank\n"); } - } else if (memSchedPolicy == Enums::fcfs) { + } else if (memSchedPolicy == enums::fcfs) { // check if there is a packet going to a free rank for (auto i = queue.begin(); i != queue.end(); ++i) { MemPacket* mem_pkt = *i; @@ -577,7 +577,7 @@ MemCtrl::chooseNext(MemPacketQueue& queue, Tick extra_col_delay) break; } } - } else if (memSchedPolicy == Enums::frfcfs) { + } else if (memSchedPolicy == enums::frfcfs) { ret = chooseNextFRFCFS(queue, extra_col_delay); } else { panic("No scheduling policy chosen\n"); diff --git a/src/mem/mem_ctrl.hh b/src/mem/mem_ctrl.hh index ec2459b917..d63e021b66 100644 --- a/src/mem/mem_ctrl.hh +++ b/src/mem/mem_ctrl.hh @@ -488,7 +488,7 @@ class MemCtrl : public qos::MemCtrl * Memory controller configuration initialized based on parameter * values. */ - Enums::MemSched memSchedPolicy; + enums::MemSched memSchedPolicy; /** * Pipeline latency of the controller frontend. The frontend diff --git a/src/mem/mem_interface.cc b/src/mem/mem_interface.cc index 9147818c8d..d3281c1158 100644 --- a/src/mem/mem_interface.cc +++ b/src/mem/mem_interface.cc @@ -101,7 +101,7 @@ MemInterface::decodePacket(const PacketPtr pkt, Addr pkt_addr, // we have removed the lowest order address bits that denote the // position within the column - if (addrMapping == Enums::RoRaBaChCo || addrMapping == Enums::RoRaBaCoCh) { + if (addrMapping == enums::RoRaBaChCo || addrMapping == enums::RoRaBaCoCh) { // the lowest order bits denote the column to ensure that // sequential cache lines occupy the same row addr = addr / burstsPerRowBuffer; @@ -118,7 +118,7 @@ MemInterface::decodePacket(const PacketPtr pkt, Addr pkt_addr, // lastly, get the row bits, no need to remove them from addr row = addr % rowsPerBank; - } else if (addrMapping == Enums::RoCoRaBaCh) { + } else if (addrMapping == enums::RoCoRaBaCh) { // with emerging technologies, could have small page size with // interleaving granularity greater than row buffer if (burstsPerStripe > burstsPerRowBuffer) { @@ -592,14 +592,14 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at, ++bank_ref.rowAccesses; // if we reached the max, then issue with an auto-precharge - bool auto_precharge = pageMgmt == Enums::close || + bool auto_precharge = pageMgmt == enums::close || bank_ref.rowAccesses == maxAccessesPerRow; // if we did not hit the limit, we might still want to // auto-precharge if (!auto_precharge && - (pageMgmt == Enums::open_adaptive || - pageMgmt == Enums::close_adaptive)) { + (pageMgmt == enums::open_adaptive || + pageMgmt == enums::close_adaptive)) { // a twist on the open and close page policies: // 1) open_adaptive page policy does not blindly keep the // page open, but close it if there are no row hits, and there @@ -642,7 +642,7 @@ DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at, // have a bank conflict // 2) close_adaptive policy and we have not got any more hits auto_precharge = !got_more_hits && - (got_bank_conflict || pageMgmt == Enums::close_adaptive); + (got_bank_conflict || pageMgmt == enums::close_adaptive); } // DRAMPower trace command to be written @@ -841,13 +841,13 @@ DRAMInterface::init() // a bit of sanity checks on the interleaving, save it for here to // ensure that the system pointer is initialised if (range.interleaved()) { - if (addrMapping == Enums::RoRaBaChCo) { + if (addrMapping == enums::RoRaBaChCo) { if (rowBufferSize != range.granularity()) { fatal("Channel interleaving of %s doesn't match RoRaBaChCo " "address map\n", name()); } - } else if (addrMapping == Enums::RoRaBaCoCh || - addrMapping == Enums::RoCoRaBaCh) { + } else if (addrMapping == enums::RoRaBaCoCh || + addrMapping == enums::RoCoRaBaCh) { // for the interleavings with channel bits in the bottom, // if the system uses a channel striping granularity that // is larger than the DRAM burst size, then map the diff --git a/src/mem/mem_interface.hh b/src/mem/mem_interface.hh index d1993acbf0..f23a08b534 100644 --- a/src/mem/mem_interface.hh +++ b/src/mem/mem_interface.hh @@ -120,7 +120,7 @@ class MemInterface : public AbstractMemory * Memory controller configuration initialized based on parameter * values. */ - Enums::AddrMap addrMapping; + enums::AddrMap addrMapping; /** * General device and channel characteristics @@ -752,7 +752,7 @@ class DRAMInterface : public MemInterface const Tick rdToWrDlySameBG; - Enums::PageManage pageMgmt; + enums::PageManage pageMgmt; /** * Max column accesses (read and write) per row, before forefully * closing it. diff --git a/src/mem/qos/q_policy.cc b/src/mem/qos/q_policy.cc index 933f16c6a5..133818d99c 100644 --- a/src/mem/qos/q_policy.cc +++ b/src/mem/qos/q_policy.cc @@ -54,11 +54,11 @@ QueuePolicy* QueuePolicy::create(const QoSMemCtrlParams &p) { switch (p.qos_q_policy) { - case Enums::QoSQPolicy::fifo: + case enums::QoSQPolicy::fifo: return new FifoQueuePolicy(p); - case Enums::QoSQPolicy::lrg: + case enums::QoSQPolicy::lrg: return new LrgQueuePolicy(p); - case Enums::QoSQPolicy::lifo: + case enums::QoSQPolicy::lifo: default: return new LifoQueuePolicy(p); } diff --git a/src/mem/ruby/network/garnet/NetworkBridge.cc b/src/mem/ruby/network/garnet/NetworkBridge.cc index db5ee7b70f..22fb229a18 100644 --- a/src/mem/ruby/network/garnet/NetworkBridge.cc +++ b/src/mem/ruby/network/garnet/NetworkBridge.cc @@ -51,10 +51,10 @@ NetworkBridge::NetworkBridge(const Params &p) lastScheduledAt = 0; nLink = p.link; - if (mType == Enums::LINK_OBJECT) { + if (mType == enums::LINK_OBJECT) { nLink->setLinkConsumer(this); setSourceQueue(nLink->getBuffer(), nLink); - } else if (mType == Enums::OBJECT_LINK) { + } else if (mType == enums::OBJECT_LINK) { nLink->setSourceQueue(&linkBuffer, this); setLinkConsumer(nLink); } else { @@ -122,7 +122,7 @@ NetworkBridge::flitisizeAndSend(flit *t_flit) // Calculate the target-width int target_width = bitWidth; int cur_width = nLink->bitWidth; - if (mType == Enums::OBJECT_LINK) { + if (mType == enums::OBJECT_LINK) { target_width = nLink->bitWidth; cur_width = bitWidth; } diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 6ee8b5c6ad..bcc2d96a3d 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -1308,7 +1308,7 @@ class MetaEnum(MetaParamValue): if cls.is_class: cls.cxx_type = '%s' % name else: - cls.cxx_type = 'Enums::%s' % name + cls.cxx_type = 'enums::%s' % name super(MetaEnum, cls).__init__(name, bases, init_dict) @@ -1366,6 +1366,7 @@ extern const char *${name}Strings[static_cast(${name}::Num_${name})]; file_name = cls.__name__ name = cls.__name__ if cls.enum_name is None else cls.enum_name + code('#include "base/compiler.hh"') code('#include "enums/$file_name.hh"') if cls.wrapper_is_struct: code('const char *${wrapper_name}::${name}Strings' @@ -1376,7 +1377,9 @@ extern const char *${name}Strings[static_cast(${name}::Num_${name})]; const char *${name}Strings[static_cast(${name}::Num_${name})] = ''') else: - code('namespace Enums {') + code('''GEM5_DEPRECATED_NAMESPACE(Enums, enums); +namespace enums +{''') code.indent(1) code('const char *${name}Strings[Num_${name}] =') @@ -1437,7 +1440,7 @@ class Enum(ParamValue, metaclass=MetaEnum): cmd_line_settable = True # The name of the wrapping namespace or struct - wrapper_name = 'Enums' + wrapper_name = 'enums' # If true, the enum is wrapped in a struct rather than a namespace wrapper_is_struct = False @@ -1468,7 +1471,7 @@ class Enum(ParamValue, metaclass=MetaEnum): code('} else if (%s == "%s") {' % (src, elem_name)) code.indent() name = cls.__name__ if cls.enum_name is None else cls.enum_name - code('%s = %s::%s;' % (dest, name if cls.is_class else 'Enums', + code('%s = %s::%s;' % (dest, name if cls.is_class else 'enums', elem_name)) code('%s true;' % ret) code.dedent() diff --git a/src/sim/power/power_model.cc b/src/sim/power/power_model.cc index 5b8a29d552..23e978ec0e 100644 --- a/src/sim/power/power_model.cc +++ b/src/sim/power/power_model.cc @@ -109,7 +109,7 @@ PowerModel::getDynamicPower() const { assert(clocked_object); - if (power_model_type == Enums::PMType::Static) { + if (power_model_type == enums::PMType::Static) { // This power model only collects static data return 0; } @@ -119,7 +119,7 @@ PowerModel::getDynamicPower() const assert(w.size() - 1 == states_pm.size()); // Make sure we have no UNDEFINED state - warn_if(w[Enums::PwrState::UNDEFINED] > 0, + warn_if(w[enums::PwrState::UNDEFINED] > 0, "SimObject in UNDEFINED power state! Power figures might be wrong!\n"); double power = 0; @@ -137,7 +137,7 @@ PowerModel::getStaticPower() const std::vector w = clocked_object->powerState->getWeights(); - if (power_model_type == Enums::PMType::Dynamic) { + if (power_model_type == enums::PMType::Dynamic) { // This power model only collects dynamic data return 0; } diff --git a/src/sim/power/power_model.hh b/src/sim/power/power_model.hh index 3a0fc64454..5ee894d124 100644 --- a/src/sim/power/power_model.hh +++ b/src/sim/power/power_model.hh @@ -159,7 +159,7 @@ class PowerModel : public SimObject ClockedObject * clocked_object; /** The type of power model - collects all power, static or dynamic only */ - Enums::PMType power_model_type; + enums::PMType power_model_type; Stats::Value dynamicPower, staticPower; }; diff --git a/src/sim/power_domain.cc b/src/sim/power_domain.cc index 159dc3530f..f9d234164a 100644 --- a/src/sim/power_domain.cc +++ b/src/sim/power_domain.cc @@ -58,8 +58,8 @@ PowerDomain::PowerDomain(const PowerDomainParams &p) : // We will assume a power domain to start in the most performant p-state // This will be corrected during startup() - leaderTargetState = Enums::PwrState::ON; - _currState = Enums::PwrState::ON; + leaderTargetState = enums::PwrState::ON; + _currState = enums::PwrState::ON; } void @@ -78,7 +78,7 @@ PowerDomain::startup() for (const auto &objs : { leaders, followers }) { for (const auto &obj : objs) { const auto & states = obj->getPossibleStates(); - auto it = states.find(Enums::PwrState::ON); + auto it = states.find(enums::PwrState::ON); fatal_if(it == states.end(), "%s in %s does not have the required power states to be " "part of a PowerDomain i.e. the ON state!", obj->name(), @@ -104,8 +104,8 @@ PowerDomain::startup() // Record the power states of the leaders and followers DPRINTF(PowerDomain, "Recording the current power states in domain\n"); for (auto leader : leaders) { - Enums::PwrState pws = leader->get(); - fatal_if(pws == Enums::PwrState::UNDEFINED, + enums::PwrState pws = leader->get(); + fatal_if(pws == enums::PwrState::UNDEFINED, "%s is in the UNDEFINED power state, not acceptable as " "leader!", leader->name()); } @@ -117,7 +117,7 @@ PowerDomain::startup() } bool -PowerDomain::isPossiblePwrState(Enums::PwrState p_state) +PowerDomain::isPossiblePwrState(enums::PwrState p_state) { for (const auto &objs : { leaders, followers }) { for (const auto &obj : objs) { @@ -138,36 +138,36 @@ PowerDomain::calculatePossiblePwrStates() if (isPossiblePwrState(p_state)) { possibleStates.emplace(p_state); DPRINTF(PowerDomain, "%u/%s is a p-state\n", p_state, - Enums::PwrStateStrings[p_state]); + enums::PwrStateStrings[p_state]); } } } -Enums::PwrState +enums::PwrState PowerDomain::calculatePowerDomainState( - const std::vector &f_states) + const std::vector &f_states) { DPRINTF(PowerDomain, "Calculating the power state\n"); - Enums::PwrState most_perf_state = Enums::PwrState::Num_PwrState; + enums::PwrState most_perf_state = enums::PwrState::Num_PwrState; std::string most_perf_leader; for (auto leader : leaders) { - Enums::PwrState pw = leader->get(); + enums::PwrState pw = leader->get(); if (pw < most_perf_state) { most_perf_state = pw; most_perf_leader = leader->name(); } } - assert(most_perf_state != Enums::PwrState::Num_PwrState); + assert(most_perf_state != enums::PwrState::Num_PwrState); DPRINTF(PowerDomain, "Most performant leader is %s, at %u\n", most_perf_leader, most_perf_state); // If asked to check the power states of the followers (f_states contains // the power states of the followers) if (!f_states.empty()) { - for (Enums::PwrState f_pw : f_states ) { + for (enums::PwrState f_pw : f_states ) { // Ignore UNDEFINED state of follower, at startup the followers // might be in the UNDEFINED state, PowerDomain will pull them up - if ((f_pw != Enums::PwrState::UNDEFINED) && + if ((f_pw != enums::PwrState::UNDEFINED) && (f_pw < most_perf_state)) { most_perf_state = f_pw; } @@ -183,9 +183,9 @@ PowerDomain::setFollowerPowerStates() { // Loop over all followers and tell them to change their power state so // they match that of the power domain (or a more performant power state) - std::vector matched_states; + std::vector matched_states; for (auto follower : followers) { - Enums::PwrState actual_pws = + enums::PwrState actual_pws = follower->matchPwrState(leaderTargetState); matched_states.push_back(actual_pws); assert(actual_pws <= leaderTargetState); @@ -195,7 +195,7 @@ PowerDomain::setFollowerPowerStates() } // Now the power states of the follower have been changed recalculate the // power state of the domain as a whole, including followers - Enums::PwrState new_power_state = + enums::PwrState new_power_state = calculatePowerDomainState(matched_states); if (new_power_state != _currState) { // Change in power state of the domain, so update. Updates in power @@ -208,13 +208,13 @@ PowerDomain::setFollowerPowerStates() } void -PowerDomain::pwrStateChangeCallback(Enums::PwrState new_pwr_state, +PowerDomain::pwrStateChangeCallback(enums::PwrState new_pwr_state, PowerState* leader) { DPRINTF(PowerDomain, "PwrState update to %u by %s\n", new_pwr_state, leader->name()); - Enums::PwrState old_target_state = leaderTargetState; + enums::PwrState old_target_state = leaderTargetState; // Calculate the power state of the domain, based on the leaders if (new_pwr_state < _currState) { // The power state of the power domain always needs to match that of diff --git a/src/sim/power_domain.hh b/src/sim/power_domain.hh index b07b6de139..a7d12d7293 100644 --- a/src/sim/power_domain.hh +++ b/src/sim/power_domain.hh @@ -73,7 +73,7 @@ class PowerDomain : public PowerState * domain will change its own power state if required and if there is a * power state, it will schedule an event to update its followers */ - void pwrStateChangeCallback(Enums::PwrState new_pwr_state, + void pwrStateChangeCallback(enums::PwrState new_pwr_state, PowerState* leader); /** @@ -92,14 +92,14 @@ class PowerDomain : public PowerState * which the followers returned when asked to match a certain power * state (called from setFollowerPowerStates) */ - Enums::PwrState calculatePowerDomainState( - const std::vector &f_states={}); + enums::PwrState calculatePowerDomainState( + const std::vector &f_states={}); /** * Check if a given p_state is available across all leaders and * followers in this domain. */ - bool isPossiblePwrState(Enums::PwrState p_state); + bool isPossiblePwrState(enums::PwrState p_state); /** * Calculate the possible power states of the domain based upon the @@ -130,7 +130,7 @@ class PowerDomain : public PowerState * power state of the domain as whole (as that one depends on the * matched power states of the followers */ - Enums::PwrState leaderTargetState; + enums::PwrState leaderTargetState; /** * List of all followers in the PowerDomain. The power state of the diff --git a/src/sim/power_state.cc b/src/sim/power_state.cc index 0e3792a2f3..3416b50127 100644 --- a/src/sim/power_state.cc +++ b/src/sim/power_state.cc @@ -85,16 +85,16 @@ PowerState::unserialize(CheckpointIn &cp) UNSERIALIZE_SCALAR(currState); UNSERIALIZE_SCALAR(prvEvalTick); - _currState = Enums::PwrState(currState); + _currState = enums::PwrState(currState); } void -PowerState::set(Enums::PwrState p) +PowerState::set(enums::PwrState p) { // Check if this power state is actually allowed by checking whether it is // present in pwrStateToIndex-dictionary panic_if(possibleStates.find(p) == possibleStates.end(), - "Cannot go to %s in %s \n", Enums::PwrStateStrings[p], name()); + "Cannot go to %s in %s \n", enums::PwrStateStrings[p], name()); // Function should ideally be called only when there is a state change if (_currState == p) { @@ -131,8 +131,8 @@ PowerState::set(Enums::PwrState p) } -Enums::PwrState -PowerState::matchPwrState(Enums::PwrState p) +enums::PwrState +PowerState::matchPwrState(enums::PwrState p) { // If the object is asked to match a power state, it has to be a follower // and hence should not have a pointer to a powerDomain @@ -141,11 +141,11 @@ PowerState::matchPwrState(Enums::PwrState p) // If we are already in this power state, ignore request if (_currState == p) { DPRINTF(PowerDomain, "Already in p-state %s requested to match \n", - Enums::PwrStateStrings[p]); + enums::PwrStateStrings[p]); return _currState; } - Enums::PwrState old_state = _currState; + enums::PwrState old_state = _currState; if (possibleStates.find(p) != possibleStates.end()) { // If this power state is allowed in this object, just go there set(p); @@ -159,8 +159,8 @@ PowerState::matchPwrState(Enums::PwrState p) // This power state is the least performant power state that is // still more performant than the requested one DPRINTF(PowerDomain, "Best match for %s is %s \n", - Enums::PwrStateStrings[p], - Enums::PwrStateStrings[*(rev_it)]); + enums::PwrStateStrings[p], + enums::PwrStateStrings[*(rev_it)]); set(*(rev_it)); break; } @@ -173,7 +173,7 @@ PowerState::matchPwrState(Enums::PwrState p) possibleStates.find(_currState) != possibleStates.begin(), "Transition to power state %s was not possible, SimObject already" " in the most performance state %s", - Enums::PwrStateStrings[p], Enums::PwrStateStrings[_currState]); + enums::PwrStateStrings[p], enums::PwrStateStrings[_currState]); stats.numPwrMatchStateTransitions++; return _currState; @@ -190,7 +190,7 @@ PowerState::computeStats() // Time spent in CLK_GATED state, this might change depending on // transition to other low power states in respective simulation // objects. - if (_currState == Enums::PwrState::CLK_GATED) { + if (_currState == enums::PwrState::CLK_GATED) { stats.ticksClkGated.sample(elapsed_time); } @@ -209,8 +209,8 @@ PowerState::getWeights() const Tick elapsed_time = curTick() - prvEvalTick; residencies[_currState] += elapsed_time; - ret.resize(Enums::PwrState::Num_PwrState); - for (unsigned i = 0; i < Enums::PwrState::Num_PwrState; i++) + ret.resize(enums::PwrState::Num_PwrState); + for (unsigned i = 0; i < enums::PwrState::Num_PwrState; i++) ret[i] = residencies[i] / \ (stats.pwrStateResidencyTicks.total() + elapsed_time); @@ -252,11 +252,11 @@ PowerState::PowerStateStats::regStats() ; pwrStateResidencyTicks - .init(Enums::PwrState::Num_PwrState) + .init(enums::PwrState::Num_PwrState) .flags(nozero) ; - for (int i = 0; i < Enums::PwrState::Num_PwrState; i++) { - pwrStateResidencyTicks.subname(i, Enums::PwrStateStrings[i]); + for (int i = 0; i < enums::PwrState::Num_PwrState; i++) { + pwrStateResidencyTicks.subname(i, enums::PwrStateStrings[i]); } numTransitions = 0; diff --git a/src/sim/power_state.hh b/src/sim/power_state.hh index b9c41d4fe3..410405722b 100644 --- a/src/sim/power_state.hh +++ b/src/sim/power_state.hh @@ -76,17 +76,17 @@ class PowerState : public SimObject /** * Change the power state of this object to the power state p */ - void set(Enums::PwrState p); + void set(enums::PwrState p); - inline Enums::PwrState get() const + inline enums::PwrState get() const { return _currState; } inline std::string getName() const { - return Enums::PwrStateStrings[_currState]; + return enums::PwrStateStrings[_currState]; } /** Returns the percentage residency for each power state */ @@ -104,12 +104,12 @@ class PowerState : public SimObject * Change the power state of this object to a power state equal to OR more * performant than p. Returns the power state the object actually went to. */ - Enums::PwrState matchPwrState(Enums::PwrState p); + enums::PwrState matchPwrState(enums::PwrState p); /** * Return the power states this object can be in */ - std::set getPossibleStates() const + std::set getPossibleStates() const { return possibleStates; } @@ -117,10 +117,10 @@ class PowerState : public SimObject protected: /** To keep track of the current power state */ - Enums::PwrState _currState; + enums::PwrState _currState; /** The possible power states this object can be in */ - std::set possibleStates; + std::set possibleStates; /** Last tick the power stats were calculated */ Tick prvEvalTick = 0; diff --git a/src/sim/system.cc b/src/sim/system.cc index e2c42a9e6a..52b322a9f4 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -275,7 +275,7 @@ System::getPort(const std::string &if_name, PortID idx) } void -System::setMemoryMode(Enums::MemoryMode mode) +System::setMemoryMode(enums::MemoryMode mode) { assert(drainState() == DrainState::Drained); memoryMode = mode; diff --git a/src/sim/system.hh b/src/sim/system.hh index cbbd5e5573..351e67e50c 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -259,8 +259,8 @@ class System : public SimObject, public PCEventScope bool isAtomicMode() const { - return memoryMode == Enums::atomic || - memoryMode == Enums::atomic_noncaching; + return memoryMode == enums::atomic || + memoryMode == enums::atomic_noncaching; } /** @@ -269,7 +269,7 @@ class System : public SimObject, public PCEventScope * SimObjects are expected to use Port::sendTiming() and * Port::recvTiming() when accessing memory in this mode. */ - bool isTimingMode() const { return memoryMode == Enums::timing; } + bool isTimingMode() const { return memoryMode == enums::timing; } /** * Should caches be bypassed? @@ -280,7 +280,7 @@ class System : public SimObject, public PCEventScope bool bypassCaches() const { - return memoryMode == Enums::atomic_noncaching; + return memoryMode == enums::atomic_noncaching; } /** @} */ @@ -292,7 +292,7 @@ class System : public SimObject, public PCEventScope * world should use one of the query functions above * (isAtomicMode(), isTimingMode(), bypassCaches()). */ - Enums::MemoryMode getMemoryMode() const { return memoryMode; } + enums::MemoryMode getMemoryMode() const { return memoryMode; } /** * Change the memory mode of the system. @@ -301,7 +301,7 @@ class System : public SimObject, public PCEventScope * * @param mode Mode to change to (atomic/timing/...) */ - void setMemoryMode(Enums::MemoryMode mode); + void setMemoryMode(enums::MemoryMode mode); /** @} */ /** @@ -413,7 +413,7 @@ class System : public SimObject, public PCEventScope PhysicalMemory physmem; - Enums::MemoryMode memoryMode; + enums::MemoryMode memoryMode; const unsigned int _cacheLineSize;