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misc: Rename Enums namespace as enums

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As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Enums became ::enums.

Change-Id: I39b5fb48817ad16abbac92f6254284b37fc90c40
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45420
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Daniel R. Carvalho
2021-05-06 16:18:58 -03:00
committed by Daniel Carvalho
parent 06fb0753fe
commit 4dd099ba3d
77 changed files with 384 additions and 381 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/amdgpu/gcn3/ast_interpreter.py
View File

@@ -755,7 +755,7 @@ class GenOne(object):
self.cg.cg_code('wf->scalarWrGmReqsInPipe--;')
self.cg.cg_code('wf->scalarOutstandingReqsWrGm++;')
elif is_flat_mem:
self.cg.cg_if('gpuDynInst->executedAs() == Enums::SC_GLOBAL')
self.cg.cg_if('gpuDynInst->executedAs() == enums::SC_GLOBAL')
self.cg.cg_code('gpuDynInst->computeUnit()->globalMemoryPipe.')
self.cg.inc_indent()
self.cg.cg_code('getGMReqFIFO().push(gpuDynInst);')

64
src/arch/amdgpu/gcn3/insts/instructions.cc
View File

@@ -36352,7 +36352,7 @@ namespace Gcn3ISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -36410,7 +36410,7 @@ namespace Gcn3ISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -39444,7 +39444,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->rdGmReqsInPipe--;
@@ -39517,7 +39517,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->rdGmReqsInPipe--;
@@ -39589,7 +39589,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->rdGmReqsInPipe--;
@@ -39690,7 +39690,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->rdGmReqsInPipe--;
@@ -39763,7 +39763,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->rdGmReqsInPipe--;
@@ -39836,7 +39836,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->rdGmReqsInPipe--;
@@ -39918,7 +39918,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->rdGmReqsInPipe--;
@@ -40000,7 +40000,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -40070,7 +40070,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -40141,7 +40141,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -40212,7 +40212,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -40283,7 +40283,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -40363,7 +40363,7 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe
.issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -40460,10 +40460,10 @@ namespace Gcn3ISA
calcAddr(gpuDynInst, addr);
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL ||
gpuDynInst->executedAs() == Enums::SC_PRIVATE) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL ||
gpuDynInst->executedAs() == enums::SC_PRIVATE) {
// TODO: additional address computation required for scratch
panic_if(gpuDynInst->executedAs() == Enums::SC_PRIVATE,
panic_if(gpuDynInst->executedAs() == enums::SC_PRIVATE,
"Flats to private aperture not tested yet\n");
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
@@ -40582,15 +40582,15 @@ namespace Gcn3ISA
}
}
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL ||
gpuDynInst->executedAs() == Enums::SC_PRIVATE) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL ||
gpuDynInst->executedAs() == enums::SC_PRIVATE) {
/**
* TODO: If you encounter this panic, just remove this panic
* and restart the simulation. It should just work fine but
* this is to warn user that this path is never tested although
* all the necessary logic is implemented
*/
panic_if(gpuDynInst->executedAs() == Enums::SC_PRIVATE,
panic_if(gpuDynInst->executedAs() == enums::SC_PRIVATE,
"Flats to private aperture not tested yet\n");
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
@@ -40688,7 +40688,7 @@ namespace Gcn3ISA
}
}
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -40785,7 +40785,7 @@ namespace Gcn3ISA
}
}
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -41056,7 +41056,7 @@ namespace Gcn3ISA
}
}
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -41153,7 +41153,7 @@ namespace Gcn3ISA
}
}
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -41283,15 +41283,15 @@ namespace Gcn3ISA
}
}
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL ||
gpuDynInst->executedAs() == Enums::SC_PRIVATE) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL ||
gpuDynInst->executedAs() == enums::SC_PRIVATE) {
/**
* TODO: If you encounter this panic, just remove this panic
* and restart the simulation. It should just work fine but
* this is to warn user that this path is never tested although
* all the necessary logic is implemented
*/
panic_if(gpuDynInst->executedAs() == Enums::SC_PRIVATE,
panic_if(gpuDynInst->executedAs() == enums::SC_PRIVATE,
"Flats to private aperture not tested yet\n");
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
@@ -41390,7 +41390,7 @@ namespace Gcn3ISA
}
}
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -41489,7 +41489,7 @@ namespace Gcn3ISA
}
}
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -41770,7 +41770,7 @@ namespace Gcn3ISA
}
}
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;
@@ -41870,7 +41870,7 @@ namespace Gcn3ISA
}
}
if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
if (gpuDynInst->executedAs() == enums::SC_GLOBAL) {
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
wf->wrGmReqsInPipe--;

2
src/arch/arm/decoder.hh
View File

@@ -78,7 +78,7 @@ class Decoder : public InstDecoder
*/
int sveLen;
Enums::DecoderFlavor decoderFlavor;
enums::DecoderFlavor decoderFlavor;
/// A cache of decoded instruction objects.
static GenericISA::BasicDecodeCache<Decoder, ExtMachInst> defaultCache;

2
src/arch/arm/isa.cc
View File

@@ -492,7 +492,7 @@ copyVecRegs(ThreadContext *src, ThreadContext *dest)
// The way vector registers are copied (VecReg vs VecElem) is relevant
// in the O3 model only.
if (src_mode == Enums::Full) {
if (src_mode == enums::Full) {
for (auto idx = 0; idx < NumVecRegs; idx++)
dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
} else {

12
src/arch/arm/isa.hh
View File

@@ -69,7 +69,7 @@ namespace ArmISA
ArmSystem *system;
// Micro Architecture
const Enums::DecoderFlavor _decoderFlavor;
const enums::DecoderFlavor _decoderFlavor;
/** Dummy device for to handle non-existing ISA devices */
DummyISADevice dummyDevice;
@@ -874,7 +874,7 @@ namespace ArmISA
void takeOverFrom(ThreadContext *new_tc,
ThreadContext *old_tc) override;
Enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
/** Returns true if the ISA has a GICv3 cpu interface */
bool haveGICv3CpuIfc() const
@@ -886,16 +886,16 @@ namespace ArmISA
return gicv3CpuInterface != nullptr;
}
Enums::VecRegRenameMode
enums::VecRegRenameMode
initVecRegRenameMode() const override
{
return highestELIs64 ? Enums::Full : Enums::Elem;
return highestELIs64 ? enums::Full : enums::Elem;
}
Enums::VecRegRenameMode
enums::VecRegRenameMode
vecRegRenameMode(ThreadContext *_tc) const override
{
return _tc->pcState().aarch64() ? Enums::Full : Enums::Elem;
return _tc->pcState().aarch64() ? enums::Full : enums::Elem;
}
PARAMS(ArmISA);

6
src/arch/generic/isa.hh
View File

@@ -68,13 +68,13 @@ class BaseISA : public SimObject
virtual bool inUserMode() const = 0;
virtual void copyRegsFrom(ThreadContext *src) = 0;
virtual Enums::VecRegRenameMode
virtual enums::VecRegRenameMode
initVecRegRenameMode() const
{
return Enums::Full;
return enums::Full;
}
virtual Enums::VecRegRenameMode
virtual enums::VecRegRenameMode
vecRegRenameMode(ThreadContext *_tc) const
{
return initVecRegRenameMode();

6
src/arch/x86/bios/intelmp.hh
View File

@@ -230,9 +230,9 @@ class IntAssignment : public BaseConfigEntry
Addr writeOut(PortProxy& proxy, Addr addr, uint8_t &checkSum);
IntAssignment(const X86IntelMPBaseConfigEntryParams &p,
Enums::X86IntelMPInterruptType _interruptType,
Enums::X86IntelMPPolarity polarity,
Enums::X86IntelMPTriggerMode trigger,
enums::X86IntelMPInterruptType _interruptType,
enums::X86IntelMPPolarity polarity,
enums::X86IntelMPTriggerMode trigger,
uint8_t _type,
uint8_t _sourceBusID, uint8_t _sourceBusIRQ,
uint8_t _destApicID, uint8_t _destApicIntIn) :