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arch-arm: Fix MCR/MRC disassemble

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This patch is fixing the Aarch32 MCR/MRC disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the coprocessor register name

Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5862
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2017-11-15 15:27:35 +00:00
parent 2a2c66c16c
commit 4d893c215e
1 changed files with 2 additions and 4 deletions
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6
src/arch/arm/insts/misc.cc
View File

@@ -259,10 +259,9 @@ MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printIntReg(ss, dest);
printMiscReg(ss, dest);
ss << ", ";
printIntReg(ss, op1);
ccprintf(ss, ", #%d", imm);
return ss.str();
}
@@ -273,8 +272,7 @@ RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
printMnemonic(ss);
printIntReg(ss, dest);
ss << ", ";
printIntReg(ss, op1);
ccprintf(ss, ", #%d", imm);
printMiscReg(ss, op1);
return ss.str();
}