ARM: Add support for switching CPUs
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@@ -43,6 +43,7 @@
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#include "dev/io_device.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "sim/system.hh"
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using namespace ArmISA;
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@@ -59,9 +60,10 @@ TableWalker::~TableWalker()
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}
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unsigned int TableWalker::drain(Event *de)
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unsigned int
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TableWalker::drain(Event *de)
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{
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if (stateQueueL1.size() != 0 || stateQueueL2.size() != 0)
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if (stateQueueL1.size() || stateQueueL2.size() || pendingQueue.size())
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{
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changeState(Draining);
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DPRINTF(Checkpoint, "TableWalker busy, wait to drain\n");
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@@ -75,6 +77,16 @@ unsigned int TableWalker::drain(Event *de)
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}
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}
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void
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TableWalker::resume()
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{
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MemObject::resume();
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if ((params()->sys->getMemoryMode() == Enums::timing) && currState) {
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delete currState;
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currState = NULL;
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}
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}
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Port*
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TableWalker::getPort(const std::string &if_name, int idx)
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{
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@@ -351,6 +351,7 @@ class TableWalker : public MemObject
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}
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virtual unsigned int drain(Event *de);
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virtual void resume();
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virtual Port *getPort(const std::string &if_name, int idx = -1);
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Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
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@@ -133,5 +133,22 @@ skipFunction(ThreadContext *tc)
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tc->pcState(newPC);
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}
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void
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copyRegs(ThreadContext *src, ThreadContext *dest)
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{
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int i;
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for(i = 0; i < TheISA::NumIntRegs; i++)
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dest->setIntReg(i, src->readIntReg(i));
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for(i = 0; i < TheISA::NumFloatRegs; i++)
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dest->setFloatReg(i, src->readFloatReg(i));
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for(i = 0; i < TheISA::NumMiscRegs; i++)
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dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
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// setMiscReg "with effect" will set the misc register mapping correctly.
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// e.g. updateRegMap(val)
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dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
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// Lastly copy PC/NPC
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dest->pcState(src->pcState());
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}
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}
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@@ -102,11 +102,7 @@ namespace ArmISA {
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tc->activate(0);
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}
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static inline void
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copyRegs(ThreadContext *src, ThreadContext *dest)
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{
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panic("Copy Regs Not Implemented Yet\n");
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}
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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static inline void
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copyMiscRegs(ThreadContext *src, ThreadContext *dest)
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