derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

kvm,arm: Update the KVM ARM v8 CPU to use vector regs.

Browse Source 
The exact mapping of the KVM registers and the gem5 registers is direct and
may not actually be correct.

Change-Id: Idb0981105c002e65755f8dfc315dbb95ea9370df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23402
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2019-12-04 22:02:30 -08:00
parent d3aba22c52
commit 4bbd03d76d
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/arch/arm/kvm/armv8_cpu.cc
View File

@@ -249,10 +249,10 @@ ArmV8KvmCPU::updateKvmState()
}
for (int i = 0; i < NUM_QREGS; ++i) {
const RegIndex reg_base(i * FP_REGS_PER_VFP_REG);
KvmFPReg reg;
auto v = tc->readVecReg(RegId(VecRegClass, i)).as<VecElem>();
for (int j = 0; j < FP_REGS_PER_VFP_REG; j++)
reg.s[j].i = tc->readFloatReg(reg_base + j);
reg.s[j].i = v[j];
setOneReg(kvmFPReg(i), reg.data);
DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i)));
@@ -321,12 +321,12 @@ ArmV8KvmCPU::updateThreadContext()
}
for (int i = 0; i < NUM_QREGS; ++i) {
const RegIndex reg_base(i * FP_REGS_PER_VFP_REG);
KvmFPReg reg;
DPRINTF(KvmContext, " Q%i: %s\n", i, getAndFormatOneReg(kvmFPReg(i)));
getOneReg(kvmFPReg(i), reg.data);
auto v = tc->getWritableVecReg(RegId(VecRegClass, i)).as<VecElem>();
for (int j = 0; j < FP_REGS_PER_VFP_REG; j++)
tc->setFloatReg(reg_base + j, reg.s[j].i);
v[j] = reg.s[j].i;
}
for (const auto &ri : getSysRegMap()) {