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arch-arm: Fix build errors with gcc 10.2

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The "-Werror=type-limits" flag in GCC 10.2 reports these errors,
because ``imm`` in neon.isa, and ``imm`` and ``count`` in sve.isa are
unsigned, and they're used to do ``imm < 0`` and ``imm * count >= 0``
comparison.

Change-Id: I33934357f578a9fc1040a6d9c08ea929fb36eb47
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33154
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Iru Cai
2020-08-21 15:11:39 +08:00
committed by Bobby R. Bruce
parent f2bda57a96
commit 4aab23e34f
2 changed files with 6 additions and 11 deletions
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6
src/arch/arm/isa/insts/neon.isa
View File

@@ -1416,7 +1416,7 @@ let {{
if readDest:
readDestCode = 'destElem = letoh(destReg.elements[i]);'
eWalkCode += '''
if (imm < 0 && imm >= eCount) {
if (imm >= eCount) {
fault = std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
} else {
@@ -1468,7 +1468,7 @@ let {{
if readDest:
readDestCode = 'destElem = letoh(destReg.elements[i]);'
eWalkCode += '''
if (imm < 0 && imm >= eCount) {
if (imm >= eCount) {
fault = std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
} else {
@@ -1518,7 +1518,7 @@ let {{
if readDest:
readDestCode = 'destReg = destRegs[i];'
eWalkCode += '''
if (imm < 0 && imm >= eCount) {
if (imm >= eCount) {
fault = std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
} else {

11
src/arch/arm/isa/insts/sve.isa
View File

@@ -4335,13 +4335,10 @@ let {{
destElem = srcElem1 - (count * imm);
bool negDest = (destElem < 0);
bool negSrc = (srcElem1 < 0);
bool posCount = ((count * imm) >= 0);
if ((negDest != negSrc) && (negSrc == posCount)) {
if (!negDest && negSrc) {
destElem = static_cast<%(dstType)s>(
(%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1)
);
if (negDest)
destElem -= 1;
}
'''
sveElemCountInst('sqdec', 'Sqdec32', 'SimdAluOp', signedTypes,
@@ -4394,13 +4391,11 @@ let {{
destElem = srcElem1 + (count * imm);
bool negDest = (destElem < 0);
bool negSrc = (srcElem1 < 0);
bool negCount = ((count * imm) < 0);
if ((negDest != negSrc) && (negSrc == negCount)) {
if (negDest && !negSrc) {
destElem = static_cast<%(dstType)s>(
(%(dstType)s)1 << (sizeof(%(dstType)s) * 8 - 1)
);
if (negDest)
destElem -= 1;
destElem -= 1;
}
'''
sveElemCountInst('sqinc', 'Sqinc32', 'SimdAluOp', signedTypes,