ARM: Set up an intregs.hh for ARM.
Add constants for all the modes and registers, maps for aliasing, functions that use the maps and range check, and use a named constant instead of a magic number for the microcode register.
This commit is contained in:
Gabe Black
326
src/arch/arm/intregs.hh
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326
src/arch/arm/intregs.hh
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@@ -0,0 +1,326 @@
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/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include <assert.h>
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#ifndef __ARCH_ARM_INTREGS_HH__
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#define __ARCH_ARM_INTREGS_HH__
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namespace ArmISA
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{
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enum IntRegIndex
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{
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/* All the unique register indices. */
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INTREG_R0,
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INTREG_R1,
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INTREG_R2,
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INTREG_R3,
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INTREG_R4,
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INTREG_R5,
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INTREG_R6,
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INTREG_R7,
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INTREG_R8,
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INTREG_R9,
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INTREG_R10,
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INTREG_R11,
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INTREG_R12,
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INTREG_R13,
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INTREG_SP = INTREG_R13,
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INTREG_R14,
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INTREG_LR = INTREG_R14,
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INTREG_R15,
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INTREG_PC = INTREG_R15,
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INTREG_R13_SVC,
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INTREG_SP_SVC = INTREG_R13_SVC,
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INTREG_R14_SVC,
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INTREG_LR_SVC = INTREG_R14_SVC,
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INTREG_R15_SVC = INTREG_R15,
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INTREG_R13_MON,
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INTREG_SP_MON = INTREG_R13_MON,
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INTREG_R14_MON,
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INTREG_LR_MON = INTREG_R14_MON,
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INTREG_R15_MON = INTREG_R15,
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INTREG_R13_ABT,
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INTREG_SP_ABT = INTREG_R13_ABT,
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INTREG_R14_ABT,
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INTREG_LR_ABT = INTREG_R14_ABT,
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INTREG_R15_ABT = INTREG_R15,
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INTREG_R13_UND,
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INTREG_SP_UND = INTREG_R13_UND,
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INTREG_R14_UND,
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INTREG_LR_UND = INTREG_R14_UND,
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INTREG_R15_UND = INTREG_R15,
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INTREG_R13_IRQ,
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INTREG_SP_IRQ = INTREG_R13_IRQ,
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INTREG_R14_IRQ,
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INTREG_LR_IRQ = INTREG_R14_IRQ,
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INTREG_R15_IRQ = INTREG_R15,
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INTREG_R8_FIQ,
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INTREG_R9_FIQ,
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INTREG_R10_FIQ,
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INTREG_R11_FIQ,
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INTREG_R12_FIQ,
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INTREG_R13_FIQ,
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INTREG_SP_FIQ = INTREG_R13_FIQ,
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INTREG_R14_FIQ,
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INTREG_LR_FIQ = INTREG_R14_FIQ,
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INTREG_R15_FIQ = INTREG_R15,
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INTREG_ZERO, // Dummy zero reg since there has to be one.
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INTREG_UREG0,
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NUM_INTREGS,
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NUM_ARCH_INTREGS = INTREG_PC + 1,
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/* All the aliased indexes. */
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/* USR mode */
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INTREG_R0_USR = INTREG_R0,
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INTREG_R1_USR = INTREG_R1,
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INTREG_R2_USR = INTREG_R2,
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INTREG_R3_USR = INTREG_R3,
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INTREG_R4_USR = INTREG_R4,
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INTREG_R5_USR = INTREG_R5,
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INTREG_R6_USR = INTREG_R6,
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INTREG_R7_USR = INTREG_R7,
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INTREG_R8_USR = INTREG_R8,
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INTREG_R9_USR = INTREG_R9,
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INTREG_R10_USR = INTREG_R10,
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INTREG_R11_USR = INTREG_R11,
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INTREG_R12_USR = INTREG_R12,
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INTREG_R13_USR = INTREG_R13,
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INTREG_SP_USR = INTREG_SP,
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INTREG_R14_USR = INTREG_R14,
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INTREG_LR_USR = INTREG_LR,
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INTREG_R15_USR = INTREG_R15,
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INTREG_PC_USR = INTREG_PC,
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/* SVC mode */
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INTREG_R0_SVC = INTREG_R0,
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INTREG_R1_SVC = INTREG_R1,
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INTREG_R2_SVC = INTREG_R2,
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INTREG_R3_SVC = INTREG_R3,
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INTREG_R4_SVC = INTREG_R4,
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INTREG_R5_SVC = INTREG_R5,
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INTREG_R6_SVC = INTREG_R6,
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INTREG_R7_SVC = INTREG_R7,
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INTREG_R8_SVC = INTREG_R8,
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INTREG_R9_SVC = INTREG_R9,
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INTREG_R10_SVC = INTREG_R10,
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INTREG_R11_SVC = INTREG_R11,
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INTREG_R12_SVC = INTREG_R12,
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INTREG_PC_SVC = INTREG_PC,
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/* MON mode */
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INTREG_R0_MON = INTREG_R0,
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INTREG_R1_MON = INTREG_R1,
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INTREG_R2_MON = INTREG_R2,
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INTREG_R3_MON = INTREG_R3,
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INTREG_R4_MON = INTREG_R4,
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INTREG_R5_MON = INTREG_R5,
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INTREG_R6_MON = INTREG_R6,
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INTREG_R7_MON = INTREG_R7,
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INTREG_R8_MON = INTREG_R8,
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INTREG_R9_MON = INTREG_R9,
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INTREG_R10_MON = INTREG_R10,
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INTREG_R11_MON = INTREG_R11,
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INTREG_R12_MON = INTREG_R12,
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INTREG_PC_MON = INTREG_PC,
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/* ABT mode */
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INTREG_R0_ABT = INTREG_R0,
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INTREG_R1_ABT = INTREG_R1,
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INTREG_R2_ABT = INTREG_R2,
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INTREG_R3_ABT = INTREG_R3,
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INTREG_R4_ABT = INTREG_R4,
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INTREG_R5_ABT = INTREG_R5,
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INTREG_R6_ABT = INTREG_R6,
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INTREG_R7_ABT = INTREG_R7,
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INTREG_R8_ABT = INTREG_R8,
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INTREG_R9_ABT = INTREG_R9,
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INTREG_R10_ABT = INTREG_R10,
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INTREG_R11_ABT = INTREG_R11,
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INTREG_R12_ABT = INTREG_R12,
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INTREG_PC_ABT = INTREG_PC,
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/* UND mode */
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INTREG_R0_UND = INTREG_R0,
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INTREG_R1_UND = INTREG_R1,
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INTREG_R2_UND = INTREG_R2,
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INTREG_R3_UND = INTREG_R3,
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INTREG_R4_UND = INTREG_R4,
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INTREG_R5_UND = INTREG_R5,
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INTREG_R6_UND = INTREG_R6,
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INTREG_R7_UND = INTREG_R7,
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INTREG_R8_UND = INTREG_R8,
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INTREG_R9_UND = INTREG_R9,
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INTREG_R10_UND = INTREG_R10,
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INTREG_R11_UND = INTREG_R11,
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INTREG_R12_UND = INTREG_R12,
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INTREG_PC_UND = INTREG_PC,
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/* IRQ mode */
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INTREG_R0_IRQ = INTREG_R0,
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INTREG_R1_IRQ = INTREG_R1,
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INTREG_R2_IRQ = INTREG_R2,
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INTREG_R3_IRQ = INTREG_R3,
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INTREG_R4_IRQ = INTREG_R4,
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INTREG_R5_IRQ = INTREG_R5,
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INTREG_R6_IRQ = INTREG_R6,
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INTREG_R7_IRQ = INTREG_R7,
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INTREG_R8_IRQ = INTREG_R8,
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INTREG_R9_IRQ = INTREG_R9,
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INTREG_R10_IRQ = INTREG_R10,
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INTREG_R11_IRQ = INTREG_R11,
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INTREG_R12_IRQ = INTREG_R12,
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INTREG_PC_IRQ = INTREG_PC,
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/* FIQ mode */
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INTREG_R0_FIQ = INTREG_R0,
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INTREG_R1_FIQ = INTREG_R1,
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INTREG_R2_FIQ = INTREG_R2,
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INTREG_R3_FIQ = INTREG_R3,
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INTREG_R4_FIQ = INTREG_R4,
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INTREG_R5_FIQ = INTREG_R5,
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INTREG_R6_FIQ = INTREG_R6,
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INTREG_R7_FIQ = INTREG_R7,
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INTREG_PC_FIQ = INTREG_PC,
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};
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typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
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const IntRegMap IntRegUsrMap = {
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INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
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INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
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INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
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INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR
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};
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static inline IntRegIndex
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INTREG_USR(unsigned index)
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{
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assert(index < NUM_ARCH_INTREGS);
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return IntRegUsrMap[index];
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}
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const IntRegMap IntRegSvcMap = {
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INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
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INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
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INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
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INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC
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};
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static inline IntRegIndex
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INTREG_SVC(unsigned index)
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{
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assert(index < NUM_ARCH_INTREGS);
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return IntRegSvcMap[index];
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}
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const IntRegMap IntRegMonMap = {
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INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
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INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
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INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
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INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON
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};
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static inline IntRegIndex
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INTREG_MON(unsigned index)
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{
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assert(index < NUM_ARCH_INTREGS);
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return IntRegMonMap[index];
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}
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const IntRegMap IntRegAbtMap = {
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INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
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INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
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INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
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INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT
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};
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static inline IntRegIndex
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INTREG_ABT(unsigned index)
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{
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assert(index < NUM_ARCH_INTREGS);
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return IntRegAbtMap[index];
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}
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const IntRegMap IntRegUndMap = {
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INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
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INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
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INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
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INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND
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};
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static inline IntRegIndex
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INTREG_UND(unsigned index)
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{
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assert(index < NUM_ARCH_INTREGS);
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return IntRegUndMap[index];
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}
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const IntRegMap IntRegIrqMap = {
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INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
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INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
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INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
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INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ
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};
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static inline IntRegIndex
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INTREG_IRQ(unsigned index)
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{
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assert(index < NUM_ARCH_INTREGS);
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return IntRegIrqMap[index];
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}
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const IntRegMap IntRegFiqMap = {
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INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
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INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
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INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
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INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ
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};
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static inline IntRegIndex
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INTREG_FIQ(unsigned index)
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{
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assert(index < NUM_ARCH_INTREGS);
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return IntRegFiqMap[index];
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}
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}
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#endif
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@@ -213,9 +213,9 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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break;
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}
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// Add 0 to Rn and stick it in Raddr (register 17).
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// Add 0 to Rn and stick it in ureg0.
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// This is equivalent to a move.
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microOps[0] = new MicroAddiUop(machInst, 17, RN, 0);
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microOps[0] = new MicroAddiUop(machInst, INTREG_UREG0, RN, 0);
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unsigned j = 0;
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for (int i = 1; i < ones+1; i++) {
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@@ -225,9 +225,11 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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regs_to_handle &= ~(1<<j);
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if (loadop)
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microOps[i] = new MicroLdrUop(machInst, j, 17, start_addr);
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microOps[i] = new MicroLdrUop(machInst, j,
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INTREG_UREG0, start_addr);
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else
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microOps[i] = new MicroStrUop(machInst, j, 17, start_addr);
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microOps[i] = new MicroStrUop(machInst, j,
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INTREG_UREG0, start_addr);
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if (up)
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start_addr += 4;
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@@ -32,6 +32,7 @@
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#define __ARCH_ARM_REGISTERS_HH__
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#include "arch/arm/max_inst_regs.hh"
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#include "arch/arm/intregs.hh"
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#include "arch/arm/miscregs.hh"
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namespace ArmISA {
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@@ -51,13 +52,12 @@ typedef float FloatReg;
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typedef uint64_t MiscReg;
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// Constants Related to the number of registers
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const int NumIntArchRegs = 16;
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const int NumIntSpecialRegs = 19;
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const int NumIntArchRegs = NUM_ARCH_INTREGS;
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const int NumFloatArchRegs = 16;
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const int NumFloatSpecialRegs = 5;
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const int NumInternalProcRegs = 0;
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const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
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const int NumIntRegs = NUM_INTREGS;
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const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
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const int NumMiscRegs = NUM_MISCREGS;
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@@ -72,11 +72,11 @@ const int ArgumentReg1 = 1;
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const int ArgumentReg2 = 2;
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const int ArgumentReg3 = 3;
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const int FramePointerReg = 11;
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const int StackPointerReg = 13;
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const int ReturnAddressReg = 14;
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const int PCReg = 15;
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const int StackPointerReg = INTREG_SP;
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const int ReturnAddressReg = INTREG_LR;
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const int PCReg = INTREG_PC;
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const int ZeroReg = NumIntArchRegs;
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const int ZeroReg = INTREG_ZERO;
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const int SyscallNumReg = ReturnValueReg;
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const int SyscallPseudoReturnReg = ReturnValueReg;
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