arch-arm: Add isStage2 qualifier to the LongDecriptor

We are currently using the LongDecriptor for both stage1
and stage2 translations. There are several cases where
the bitfield meaning changes depending on the translation
stage.

Change-Id: Ic33d9ef225a57fd79ce2b4bf47896aeb6bdd8d9c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/arch/arm/table_walker.cc

@@ -843,6 +843,7 @@ TableWalker::processWalkLPAE()
     currState->longDesc.lookupLevel = start_lookup_level;
     currState->longDesc.aarch64 = false;
     currState->longDesc.grainSize = Grain4KB;
+    currState->longDesc.isStage2 = isStage2;
 
     fetchDescriptor(
         desc_addr, currState->longDesc,
@@ -1095,6 +1096,7 @@ TableWalker::processWalkAArch64()
     currState->longDesc.aarch64 = true;
     currState->longDesc.grainSize = tg;
     currState->longDesc.physAddrRange = _physAddrRange;
+    currState->longDesc.isStage2 = isStage2;
 
     fetchDescriptor(desc_addr, currState->longDesc,
                     sizeof(uint64_t), flag, start_lookup_level,

src/arch/arm/table_walker.hh

@@ -436,7 +436,7 @@ class TableWalker : public ClockedObject
 
         LongDescriptor()
           : data(0), _dirty(false), aarch64(false), grainSize(Grain4KB),
-            physAddrRange(0)
+            physAddrRange(0), isStage2(false)
         {}
 
         /** The raw bits of the entry */
@@ -454,6 +454,8 @@ class TableWalker : public ClockedObject
 
         uint8_t physAddrRange;
 
+        bool isStage2;
+
         uint8_t*
         getRawPtr() override
         {