derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes more neutral names.

Browse Source 
--HG--
extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4
This commit is contained in:
Gabe Black
2006-10-31 02:08:44 -05:00
parent 79d4bede42
commit 4862879a94
8 changed files with 600 additions and 586 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1010
src/arch/alpha/tlb.cc
View File

File diff suppressed because it is too large Load Diff

128
src/arch/alpha/tlb.hh
View File

@@ -36,6 +36,7 @@
#include "arch/alpha/ev5.hh"
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/pagetable.hh"
#include "arch/alpha/utility.hh"
#include "arch/alpha/vtophys.hh"
#include "base/statistics.hh"
@@ -45,82 +46,87 @@
class ThreadContext;
class AlphaTLB : public SimObject
namespace AlphaISA
{
protected:
typedef std::multimap<Addr, int> PageTable;
PageTable lookupTable; // Quick lookup into page table
class PTE;
AlphaISA::PTE *table; // the Page Table
int size; // TLB Size
int nlu; // not last used entry (for replacement)
class TLB : public SimObject
{
protected:
typedef std::multimap<Addr, int> PageTable;
PageTable lookupTable; // Quick lookup into page table
void nextnlu() { if (++nlu >= size) nlu = 0; }
AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
PTE *table; // the Page Table
int size; // TLB Size
int nlu; // not last used entry (for replacement)
public:
AlphaTLB(const std::string &name, int size);
virtual ~AlphaTLB();
void nextnlu() { if (++nlu >= size) nlu = 0; }
PTE *lookup(Addr vpn, uint8_t asn) const;
int getsize() const { return size; }
public:
TLB(const std::string &name, int size);
virtual ~TLB();
AlphaISA::PTE &index(bool advance = true);
void insert(Addr vaddr, AlphaISA::PTE &pte);
int getsize() const { return size; }
void flushAll();
void flushProcesses();
void flushAddr(Addr addr, uint8_t asn);
PTE &index(bool advance = true);
void insert(Addr vaddr, PTE &pte);
// static helper functions... really EV5 VM traits
static bool validVirtualAddress(Addr vaddr) {
// unimplemented bits must be all 0 or all 1
Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
}
void flushAll();
void flushProcesses();
void flushAddr(Addr addr, uint8_t asn);
static Fault checkCacheability(RequestPtr &req);
// static helper functions... really EV5 VM traits
static bool validVirtualAddress(Addr vaddr) {
// unimplemented bits must be all 0 or all 1
Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
}
// Checkpointing
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
static Fault checkCacheability(RequestPtr &req);
class AlphaITB : public AlphaTLB
{
protected:
mutable Stats::Scalar<> hits;
mutable Stats::Scalar<> misses;
mutable Stats::Scalar<> acv;
mutable Stats::Formula accesses;
// Checkpointing
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
public:
AlphaITB(const std::string &name, int size);
virtual void regStats();
class ITB : public TLB
{
protected:
mutable Stats::Scalar<> hits;
mutable Stats::Scalar<> misses;
mutable Stats::Scalar<> acv;
mutable Stats::Formula accesses;
Fault translate(RequestPtr &req, ThreadContext *tc) const;
};
public:
ITB(const std::string &name, int size);
virtual void regStats();
class AlphaDTB : public AlphaTLB
{
protected:
mutable Stats::Scalar<> read_hits;
mutable Stats::Scalar<> read_misses;
mutable Stats::Scalar<> read_acv;
mutable Stats::Scalar<> read_accesses;
mutable Stats::Scalar<> write_hits;
mutable Stats::Scalar<> write_misses;
mutable Stats::Scalar<> write_acv;
mutable Stats::Scalar<> write_accesses;
Stats::Formula hits;
Stats::Formula misses;
Stats::Formula acv;
Stats::Formula accesses;
Fault translate(RequestPtr &req, ThreadContext *tc) const;
};
public:
AlphaDTB(const std::string &name, int size);
virtual void regStats();
class DTB : public TLB
{
protected:
mutable Stats::Scalar<> read_hits;
mutable Stats::Scalar<> read_misses;
mutable Stats::Scalar<> read_acv;
mutable Stats::Scalar<> read_accesses;
mutable Stats::Scalar<> write_hits;
mutable Stats::Scalar<> write_misses;
mutable Stats::Scalar<> write_acv;
mutable Stats::Scalar<> write_accesses;
Stats::Formula hits;
Stats::Formula misses;
Stats::Formula acv;
Stats::Formula accesses;
Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
};
public:
DTB(const std::string &name, int size);
virtual void regStats();
Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
};
}
#endif // __ALPHA_MEMORY_HH__

4
src/cpu/simple/atomic.cc
View File

@@ -513,8 +513,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
Param<int> cpu_id;
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
#else
SimObjectParam<Process *> workload;

11
src/cpu/simple/base.hh
View File

@@ -47,8 +47,11 @@
// forward declarations
#if FULL_SYSTEM
class Processor;
class AlphaITB;
class AlphaDTB;
namespace TheISA
{
class ITB;
class DTB;
}
class MemObject;
class RemoteGDB;
@@ -97,8 +100,8 @@ class BaseSimpleCPU : public BaseCPU
{
MemObject *mem;
#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
TheISA::ITB *itb;
TheISA::DTB *dtb;
#else
Process *process;
#endif

4
src/cpu/simple/timing.cc
View File

@@ -665,8 +665,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
Param<int> cpu_id;
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
#else
SimObjectParam<Process *> workload;

2
src/cpu/simple_thread.cc
View File

@@ -60,7 +60,7 @@ using namespace std;
// constructor
#if FULL_SYSTEM
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
AlphaITB *_itb, AlphaDTB *_dtb,
TheISA::ITB *_itb, TheISA::DTB *_dtb,
bool use_kernel_stats)
: ThreadState(-1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
dtb(_dtb)

10
src/cpu/simple_thread.hh
View File

@@ -107,14 +107,14 @@ class SimpleThread : public ThreadState
System *system;
#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
TheISA::ITB *itb;
TheISA::DTB *dtb;
#endif
// constructor: initialize SimpleThread from given process structure
#if FULL_SYSTEM
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
AlphaITB *_itb, AlphaDTB *_dtb,
TheISA::ITB *_itb, TheISA::DTB *_dtb,
bool use_kernel_stats = true);
#else
SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid,
@@ -201,9 +201,9 @@ class SimpleThread : public ThreadState
#if FULL_SYSTEM
System *getSystemPtr() { return system; }
AlphaITB *getITBPtr() { return itb; }
TheISA::ITB *getITBPtr() { return itb; }
AlphaDTB *getDTBPtr() { return dtb; }
TheISA::DTB *getDTBPtr() { return dtb; }
FunctionalPort *getPhysPort() { return physPort; }

17
src/cpu/thread_context.hh
View File

@@ -31,9 +31,9 @@
#ifndef __CPU_THREAD_CONTEXT_HH__
#define __CPU_THREAD_CONTEXT_HH__
#include "arch/types.hh"
#include "arch/regfile.hh"
#include "arch/syscallreturn.hh"
#include "arch/types.hh"
#include "config/full_system.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
@@ -43,8 +43,11 @@
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.
class AlphaDTB;
class AlphaITB;
namespace TheISA
{
class DTB;
class ITB;
}
class BaseCPU;
class EndQuiesceEvent;
class Event;
@@ -117,9 +120,9 @@ class ThreadContext
#if FULL_SYSTEM
virtual System *getSystemPtr() = 0;
virtual AlphaITB *getITBPtr() = 0;
virtual TheISA::ITB *getITBPtr() = 0;
virtual AlphaDTB * getDTBPtr() = 0;
virtual TheISA::DTB *getDTBPtr() = 0;
virtual Kernel::Statistics *getKernelStats() = 0;
@@ -292,9 +295,9 @@ class ProxyThreadContext : public ThreadContext
#if FULL_SYSTEM
System *getSystemPtr() { return actualTC->getSystemPtr(); }
AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }