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ARM: Implement the VFP version of vadd.

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Gabe Black
2010-06-02 12:58:14 -05:00
parent 9e32ff3491
commit 44759669aa
2 changed files with 44 additions and 1 deletions
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20
src/arch/arm/isa/formats/fp.isa
View File

@@ -510,7 +510,25 @@ let {{
return new WarnUnimplemented("vnmla, vnmls, vnmul", machInst);
case 0x3:
if ((opc3 & 0x1) == 0) {
return new WarnUnimplemented("vadd", machInst);
uint32_t vd;
uint32_t vm;
uint32_t vn;
if (bits(machInst, 8) == 0) {
vd = bits(machInst, 22) | (bits(machInst, 15, 12) << 1);
vm = bits(machInst, 5) | (bits(machInst, 3, 0) << 1);
vn = bits(machInst, 7) | (bits(machInst, 19, 16) << 1);
return new VaddS(machInst, (IntRegIndex)vd,
(IntRegIndex)vn, (IntRegIndex)vm);
} else {
vd = (bits(machInst, 22) << 5) |
(bits(machInst, 15, 12) << 1);
vm = (bits(machInst, 5) << 5) |
(bits(machInst, 3, 0) << 1);
vn = (bits(machInst, 7) << 5) |
(bits(machInst, 19, 16) << 1);
return new VaddD(machInst, (IntRegIndex)vd,
(IntRegIndex)vn, (IntRegIndex)vm);
}
} else {
return new WarnUnimplemented("vsub", machInst);
}

25
src/arch/arm/isa/insts/fp.isa
View File

@@ -306,4 +306,29 @@ let {{
header_output += RegRegOpDeclare.subst(vabsDIop);
decoder_output += RegRegOpConstructor.subst(vabsDIop);
exec_output += PredOpExecute.subst(vabsDIop);
vaddSCode = '''
FpDest = FpOp1 + FpOp2;
'''
vaddSIop = InstObjParams("vadds", "VaddS", "RegRegRegOp",
{ "code": vaddSCode,
"predicate_test": predicateTest }, [])
header_output += RegRegRegOpDeclare.subst(vaddSIop);
decoder_output += RegRegRegOpConstructor.subst(vaddSIop);
exec_output += PredOpExecute.subst(vaddSIop);
vaddDCode = '''
IntDoubleUnion cOp1, cOp2, cDest;
cOp1.bits = ((uint64_t)FpOp1P0.uw | ((uint64_t)FpOp1P1.uw << 32));
cOp2.bits = ((uint64_t)FpOp2P0.uw | ((uint64_t)FpOp2P1.uw << 32));
cDest.fp = cOp1.fp + cOp2.fp;
FpDestP0.uw = cDest.bits;
FpDestP1.uw = cDest.bits >> 32;
'''
vaddDIop = InstObjParams("vaddd", "VaddD", "RegRegRegOp",
{ "code": vaddDCode,
"predicate_test": predicateTest }, [])
header_output += RegRegRegOpDeclare.subst(vaddDIop);
decoder_output += RegRegRegOpConstructor.subst(vaddDIop);
exec_output += PredOpExecute.subst(vaddDIop);
}};