stdlib: Fix LupvBoard to inherit from AbstractSystemBoard

In this patch:
https://gem5-review.googlesource.com/c/public/gem5/+/58909, the
AbstractBoard was refactored. While all otherboards were updated
correctly, the LupvBoard was not. This caused the nightly tests to
fail: https://jenkins.gem5.org/job/nightly/240

This patch corrects this issue.

Change-Id: Icac39d48358daf4acb2f7077f5d3e8871320812e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60095
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Bobby R. Bruce
2022-05-27 18:04:48 -07:00
committed by Bobby Bruce
parent d7f5b70576
commit 424b946d16

View File

@@ -28,7 +28,7 @@ import os
from typing import List
from ....utils.override import overrides
from ..abstract_board import AbstractBoard
from ..abstract_system_board import AbstractSystemBoard
from ...processors.abstract_processor import AbstractProcessor
from ...memory.abstract_memory_system import AbstractMemorySystem
from ...cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
@@ -72,7 +72,7 @@ from m5.util.fdthelper import (
FdtState,
)
class LupvBoard(AbstractBoard, KernelDiskWorkload):
class LupvBoard(AbstractSystemBoard, KernelDiskWorkload):
"""
A board capable of full system simulation for RISC-V.
This board uses a set of LupIO education-friendly devices.
@@ -100,7 +100,7 @@ class LupvBoard(AbstractBoard, KernelDiskWorkload):
super().__init__(clk_freq, processor, memory, cache_hierarchy)
@overrides(AbstractBoard)
@overrides(AbstractSystemBoard)
def _setup_board(self) -> None:
self.workload = RiscvLinux()
@@ -245,22 +245,22 @@ class LupvBoard(AbstractBoard, KernelDiskWorkload):
uncacheable=uncacheable_range
)
@overrides(AbstractBoard)
@overrides(AbstractSystemBoard)
def has_dma_ports(self) -> bool:
return False
@overrides(AbstractBoard)
@overrides(AbstractSystemBoard)
def get_dma_ports(self) -> List[Port]:
raise NotImplementedError(
"The LupvBoard does not have DMA Ports. "
"Use `has_dma_ports()` to check this."
)
@overrides(AbstractBoard)
@overrides(AbstractSystemBoard)
def has_io_bus(self) -> bool:
return True
@overrides(AbstractBoard)
@overrides(AbstractSystemBoard)
def get_io_bus(self) -> IOXBar:
return self.iobus
@@ -270,7 +270,7 @@ class LupvBoard(AbstractBoard, KernelDiskWorkload):
def get_mem_side_coherent_io_port(self) -> Port:
return self.iobus.mem_side_ports
@overrides(AbstractBoard)
@overrides(AbstractSystemBoard)
def _setup_memory_ranges(self):
memory = self.get_memory()
mem_size = memory.get_size()