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misc: Collapse all uses of DTRACE(x) to Debug::x.

Browse Source 
Also mark the DTRACE macro as deprecated.

Change-Id: I99d9a9544b539117b375186e3e425d73d3c5cab7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45009
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
This commit is contained in:
Gabe Black
2021-04-29 22:47:31 -07:00
parent 2af00af0f6
commit 41d934cf18
38 changed files with 63 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/base.cc
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@@ -579,7 +579,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
/* This code no longer works since the zero register (e.g.,
* r31 on Alpha) doesn't necessarily contain zero at this
* point.
if (DTRACE(Context))
if (Debug::Context)
ThreadContext::compare(oldTC, newTC);
*/

2
src/cpu/kvm/base.cc
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@@ -279,7 +279,7 @@ BaseKvmCPU::StatGroup::StatGroup(Stats::Group *parent)
void
BaseKvmCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
{
if (DTRACE(Checkpoint)) {
if (Debug::Checkpoint) {
DPRINTF(Checkpoint, "KVM: Serializing thread %i:\n", tid);
dump();
}

4
src/cpu/kvm/x86_cpu.cc
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@@ -682,7 +682,7 @@ X86KvmCPU::updateKvmState()
updateKvmStateMSRs();
DPRINTF(KvmContext, "X86KvmCPU::updateKvmState():\n");
if (DTRACE(KvmContext))
if (Debug::KvmContext)
dump();
}
@@ -946,7 +946,7 @@ X86KvmCPU::updateThreadContext()
getSpecialRegisters(sregs);
DPRINTF(KvmContext, "X86KvmCPU::updateThreadContext():\n");
if (DTRACE(KvmContext))
if (Debug::KvmContext)
dump();
updateThreadContextRegs(regs, sregs);

6
src/cpu/minor/execute.cc
View File

@@ -779,7 +779,7 @@ Execute::issue(ThreadID thread_id)
if (issued) {
/* Generate MinorTrace's MinorInst lines. Do this at commit
* to allow better instruction annotation? */
if (DTRACE(MinorTrace) && !inst->isBubble()) {
if (Debug::MinorTrace && !inst->isBubble()) {
inst->minorTraceInst(*this,
cpu.threads[0]->getIsaPtr()->regClasses());
}
@@ -985,7 +985,7 @@ Execute::commitInst(MinorDynInstPtr inst, bool early_memory_issue,
if (fault != NoFault) {
if (inst->traceData) {
if (DTRACE(ExecFaulting)) {
if (Debug::ExecFaulting) {
inst->traceData->setFaulting(true);
} else {
delete inst->traceData;
@@ -1389,7 +1389,7 @@ Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard,
/* Don't show no cost instructions as having taken a commit
* slot */
if (DTRACE(MinorTrace) && !is_no_cost_inst)
if (Debug::MinorTrace && !is_no_cost_inst)
ex_info.instsBeingCommitted.insts[num_insts_committed] = inst;
if (!is_no_cost_inst)

4
src/cpu/minor/fetch1.cc
View File

@@ -254,7 +254,7 @@ Fetch1::handleTLBResponse(FetchRequestPtr response)
response->request->getPaddr() : 0),
response->request->getVaddr());
if (DTRACE(MinorTrace))
if (Debug::MinorTrace)
minorTraceResponseLine(name(), response);
} else {
DPRINTF(Fetch, "Got ITLB response\n");
@@ -423,7 +423,7 @@ Fetch1::recvTimingResp(PacketPtr response)
numFetchesInMemorySystem--;
fetch_request->state = FetchRequest::Complete;
if (DTRACE(MinorTrace))
if (Debug::MinorTrace)
minorTraceResponseLine(name(), fetch_request);
if (response->isError()) {

2
src/cpu/minor/fetch2.cc
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@@ -489,7 +489,7 @@ Fetch2::evaluate()
/* Output MinorTrace instruction info for
* pre-microop decomposition macroops */
if (DTRACE(MinorTrace) && !dyn_inst->isFault() &&
if (Debug::MinorTrace && !dyn_inst->isFault() &&
dyn_inst->staticInst->isMacroop())
{
dyn_inst->minorTraceInst(*this,

2
src/cpu/minor/func_unit.cc
View File

@@ -105,7 +105,7 @@ FUPipeline::FUPipeline(const std::string &name, const MinorFU &description_,
for (unsigned int i = 0; i < description.timings.size(); i++) {
MinorFUTiming &timing = *(description.timings[i]);
if (DTRACE(MinorTiming)) {
if (Debug::MinorTiming) {
std::ostringstream lats;
unsigned int num_lats = timing.srcRegsRelativeLats.size();

2
src/cpu/minor/pipeline.cc
View File

@@ -132,7 +132,7 @@ Pipeline::evaluate()
fetch2.evaluate();
fetch1.evaluate();
if (DTRACE(MinorTrace))
if (Debug::MinorTrace)
minorTrace();
/* Update the time buffers after the stages */

2
src/cpu/minor/scoreboard.cc
View File

@@ -260,7 +260,7 @@ Scoreboard::canInstIssue(MinorDynInstPtr inst,
src_index++;
}
if (DTRACE(MinorTiming)) {
if (Debug::MinorTiming) {
if (ret && num_srcs > num_relative_latencies &&
num_relative_latencies != 0)
{

4
src/cpu/o3/commit_impl.hh
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@@ -1312,7 +1312,7 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
if (head_inst->traceData) {
// We ignore ReExecution "faults" here as they are not real
// (architectural) faults but signal flush/replays.
if (DTRACE(ExecFaulting)
if (Debug::ExecFaulting
&& dynamic_cast<ReExec*>(inst_fault.get()) == nullptr) {
head_inst->traceData->setFaulting(true);
@@ -1362,7 +1362,7 @@ DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
rob->retireHead(tid);
#if TRACING_ON
if (DTRACE(O3PipeView)) {
if (Debug::O3PipeView) {
head_inst->commitTick = curTick() - head_inst->fetchTick;
}
#endif

2
src/cpu/o3/decode_impl.hh
View File

@@ -700,7 +700,7 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
--insts_available;
#if TRACING_ON
if (DTRACE(O3PipeView)) {
if (Debug::O3PipeView) {
inst->decodeTick = curTick() - inst->fetchTick;
}
#endif

2
src/cpu/o3/dyn_inst.cc
View File

@@ -93,7 +93,7 @@ BaseO3DynInst::BaseO3DynInst(const StaticInstPtr &_staticInst,
BaseO3DynInst::~BaseO3DynInst()
{
#if TRACING_ON
if (DTRACE(O3PipeView)) {
if (Debug::O3PipeView) {
Tick fetch = this->fetchTick;
// fetchTick can be -1 if the instruction fetched outside the trace
// window.

2
src/cpu/o3/fetch_impl.hh
View File

@@ -1299,7 +1299,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
numInst++;
#if TRACING_ON
if (DTRACE(O3PipeView)) {
if (Debug::O3PipeView) {
instruction->fetchTick = curTick();
}
#endif

2
src/cpu/o3/iew_impl.hh
View File

@@ -1603,7 +1603,7 @@ DefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst)
iewStats.executedInstStats.numInsts++;
#if TRACING_ON
if (DTRACE(O3PipeView)) {
if (Debug::O3PipeView) {
inst->completeTick = curTick() - inst->fetchTick;
}
#endif

2
src/cpu/o3/lsq_unit_impl.hh
View File

@@ -1186,7 +1186,7 @@ LSQUnit<Impl>::completeStore(typename StoreQueue::iterator store_idx)
store_inst->seqNum, store_idx.idx() - 1, storeQueue.head() - 1);
#if TRACING_ON
if (DTRACE(O3PipeView)) {
if (Debug::O3PipeView) {
store_inst->storeTick =
curTick() - store_inst->fetchTick;
}

4
src/cpu/o3/mem_dep_unit_impl.hh
View File

@@ -178,7 +178,7 @@ MemDepUnit<MemDepPred, Impl>::insertBarrierSN(const DynInstPtr &barr_inst)
if (barr_inst->isWriteBarrier() || barr_inst->isHtmCmd())
storeBarrierSNs.insert(barr_sn);
if (DTRACE(MemDepUnit)) {
if (Debug::MemDepUnit) {
const char *barrier_type = nullptr;
if (barr_inst->isReadBarrier() && barr_inst->isWriteBarrier())
barrier_type = "memory";
@@ -460,7 +460,7 @@ MemDepUnit<MemDepPred, Impl>::completeInst(const DynInstPtr &inst)
assert(hasLoadBarrier());
loadBarrierSNs.erase(barr_sn);
}
if (DTRACE(MemDepUnit)) {
if (Debug::MemDepUnit) {
const char *barrier_type = nullptr;
if (inst->isWriteBarrier() && inst->isReadBarrier())
barrier_type = "Memory";

2
src/cpu/o3/rename_impl.hh
View File

@@ -807,7 +807,7 @@ DefaultRename<Impl>::sortInsts()
const DynInstPtr &inst = fromDecode->insts[i];
insts[inst->threadNumber].push_back(inst);
#if TRACING_ON
if (DTRACE(O3PipeView)) {
if (Debug::O3PipeView) {
inst->renameTick = curTick() - inst->fetchTick;
}
#endif

2
src/cpu/profile.hh
View File

@@ -86,7 +86,7 @@ class BaseStackTrace
const std::vector<Addr> &getstack() const { return stack; }
void dprintf() { if (DTRACE(Stack)) dump(); }
void dprintf() { if (Debug::Stack) dump(); }
// This function can be overridden so that special addresses which don't
// actually refer to PCs can be translated into special names. For

2
src/cpu/simple/base.cc
View File

@@ -246,7 +246,7 @@ BaseSimpleCPU::wakeup(ThreadID tid)
void
BaseSimpleCPU::traceFault()
{
if (DTRACE(ExecFaulting)) {
if (Debug::ExecFaulting) {
traceData->setFaulting(true);
} else {
delete traceData;

6
src/cpu/trace/trace_cpu.cc
View File

@@ -257,7 +257,7 @@ TraceCPU::ElasticDataGen::init()
depGraph.size());
// Print readyList
if (DTRACE(TraceCPUData)) {
if (Debug::TraceCPUData) {
printReadyList();
}
auto free_itr = readyList.begin();
@@ -509,7 +509,7 @@ TraceCPU::ElasticDataGen::execute()
} // end of while loop
// Print readyList, sizes of queues and resource status after updating
if (DTRACE(TraceCPUData)) {
if (Debug::TraceCPUData) {
printReadyList();
DPRINTF(TraceCPUData, "Execute end occupancy:\n");
DPRINTFR(TraceCPUData, "\tdepGraph = %d, readyList = %d, "
@@ -713,7 +713,7 @@ TraceCPU::ElasticDataGen::completeMemAccess(PacketPtr pkt)
depGraph.erase(graph_itr);
}
if (DTRACE(TraceCPUData)) {
if (Debug::TraceCPUData) {
printReadyList();
}