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arch-riscv: Fix RVV instructions vmv.s.x/vfmv.s.f (#843)

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This commit fixes the implementation of vmv.s.x and vfmv.s.f. 
When vl = 0, no elements are updated in the destination vector register
group, regardless of vstart.

Change-Id: Ib21b3125da8009325743ec70ca0874704328356c

Reference:
[Integer Scalar Move
Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#161-integer-scalar-move-instructions)
[Floating-Point Scalar Move
Instructions](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#162-floating-point-scalar-move-instructions)
This commit is contained in:
Chong-Teng Wang
2024-02-06 00:51:42 +08:00
committed by GitHub
parent 85059a369e
commit 40ecdf5fb4
1 changed files with 7 additions and 3 deletions
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10
src/arch/riscv/isa/decoder.isa
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@@ -4019,8 +4019,10 @@ decode QUADRANT default Unknown::unknown() {
// The encodings corresponding to the masked versions
// (vm=0) of vfmv.s.f are reserved
0x1: VectorNonSplitFormat::vfmv_s_f({{
auto fd = ftype_freg<et>(freg(Fs1_bits));
Vd_vu[0] = fd.v;
if (this->vl) {
auto fd = ftype_freg<et>(freg(Fs1_bits));
Vd_vu[0] = fd.v;
}
}}, OPFVV, VectorMiscOp);
}
}
@@ -4296,7 +4298,9 @@ decode QUADRANT default Unknown::unknown() {
// The encodings corresponding to the masked versions
// (vm=0) of vmv.s.x are reserved.
0x1: VectorNonSplitFormat::vmv_s_x({{
Vd_vu[0] = Rs1_vu;
if (this->vl) {
Vd_vu[0] = Rs1_vu;
}
}}, OPMVX, VectorMiscOp);
}
}