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arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMU

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The PMU model currently doesn't calculate the PMU event counter index
correctly for writes to the PMEVTYPER[0-5]_EL0 registers. Fix this
obvious mistake.

Change-Id: I2913eedddeb98480660e2d63948f6d727adf5ab8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3121
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
This commit is contained in:
Andreas Sandberg
2017-05-02 17:26:34 +01:00
parent 642818f1f3
commit 3f835d88a3
1 changed files with 1 additions and 1 deletions
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2
src/arch/arm/pmu.cc
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@@ -163,7 +163,7 @@ PMU::setMiscReg(int misc_reg, MiscReg val)
return;
case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:
setCounterTypeRegister(misc_reg - MISCREG_PMEVCNTR0_EL0, val);
setCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0_EL0, val);
return;
case MISCREG_PMCCFILTR: