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misc: Run pre-commit autoupdate (#419)

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1. Runs `pre-commit autoupdate`.
2. Runs `pre-commit run --all-files`.
3. Adds (2.) to ".git-blame-ignore-rev".
This commit is contained in:
Bobby R. Bruce
2023-10-10 21:41:33 -07:00
committed by GitHub
parent d559c24ac2 1502f7c09f
commit 3f5d7d647a
185 changed files with 125 additions and 177 deletions
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2
util/checkpoint_aggregator.py
View File

@@ -57,7 +57,7 @@ def aggregate(output_dir, cpts, no_compress, memory_size):
max_curtick = 0
num_digits = len(str(len(cpts) - 1))
for (i, arg) in enumerate(cpts):
for i, arg in enumerate(cpts):
print(arg)
merged_config = myCP()
config = myCP()

2
util/cpt_upgraders/arm-ccregs.py
View File

@@ -11,7 +11,7 @@ def upgrader(cpt):
continue
items = []
for (item, value) in cpt.items(sec):
for item, value in cpt.items(sec):
items.append(item)
if "ccRegs" not in items:
intRegs = cpt.get(sec, "intRegs").split()

1
util/cpt_upgraders/arm-gicv2-banked-regs.py
View File

@@ -33,6 +33,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# duplicate banked registers into new per-cpu arrays.
def upgrader(cpt):
if cpt.get("root", "isa", fallback="") == "arm":

1
util/cpt_upgraders/arm-sve.py
View File

@@ -13,7 +13,6 @@ def upgrader(cpt):
# Search for all ISA sections
if re.search(".*sys.*\.cpu.*\.isa$", sec):
# haveSVE = false
cpt.set(sec, "haveSVE", "false")

1
util/cpt_upgraders/arm-sysreg-mapping-ns.py
View File

@@ -33,6 +33,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# reflect updated register mappings for ARM ISA
def upgrader(cpt):
if cpt.get("root", "isa", fallback="") == "arm":

8
util/cpt_upgraders/isa-is-simobject.py
View File

@@ -75,17 +75,17 @@ def upgrader(cpt):
isa_section = []
for fspec in isa_fields:
for (key, value) in cpt.items(sec, raw=True):
for key, value in cpt.items(sec, raw=True):
if key in isa_fields:
isa_section.append((key, value))
name = f"{re_cpu_match.group(1)}.isa"
isa_sections.append((name, isa_section))
for (key, value) in isa_section:
for key, value in isa_section:
cpt.remove_option(sec, key)
for (sec, options) in isa_sections:
for sec, options in isa_sections:
# Some intermediate versions of gem5 have empty ISA sections
# (after we made the ISA a SimObject, but before we started to
# serialize into a separate ISA section).
@@ -97,7 +97,7 @@ def upgrader(cpt):
"Unexpected populated ISA section in old checkpoint"
)
for (key, value) in options:
for key, value in options:
cpt.set(sec, key, value)

1
util/cpt_upgraders/mempool-sections.py
View File

@@ -12,7 +12,6 @@ def upgrader(cpt):
systems[sec] = ptrs, limits
for sec, (ptrs, limits) in systems.items():
ptrs = list(map(int, ptrs.split()))
limits = list(map(int, limits.split()))

2
util/cpt_upgraders/riscv-pcstate.py
View File

@@ -26,7 +26,6 @@
def upgrader(cpt):
# Update the RISC-V pcstate to match the new version of
# PCState
@@ -34,7 +33,6 @@ def upgrader(cpt):
import re
if re.search(".*processor.*\.core.*\.xc.*", sec):
if cpt.get(sec, "_rvType", fallback="") == "":
cpt.set(sec, "_rvType", "1")

2
util/cpt_upgraders/riscv-vext.py
View File

@@ -40,7 +40,6 @@ def upgrader(cpt):
# Search for all XC sections
if re.search(".*processor.*\.core.*\.xc.*", sec):
# Updating RVV vector registers (dummy values)
# Assuming VLEN = 256 bits (32 bytes)
mr = cpt.get(sec, "regs.vector").split()
@@ -58,7 +57,6 @@ def upgrader(cpt):
# Search for all ISA sections
if re.search(".*processor.*\.core.*\.isa$", sec):
# Updating RVV misc registers (dummy values)
mr = cpt.get(sec, "miscRegFile").split()
if len(mr) == 164:

1
util/gem5art/artifact/gem5art/artifact/artifact.py
View File

@@ -166,7 +166,6 @@ class Artifact:
version: str = "",
**kwargs: str,
) -> "Artifact":
"""Constructs a new artifact without using the database.
Different from registerArtifact(), this method won't use database.

1
util/gem5art/artifact/tests/test_artifact.py
View File

@@ -205,7 +205,6 @@ class TestArtifactSimilarity(unittest.TestCase):
class TestRegisterArtifact(unittest.TestCase):
def setUp(self):
# Create and register an artifact
self.testArtifactA = artifact.Artifact.registerArtifact(
name="artifact-A",

1
util/gem5art/run/bin/gem5art-getruns
View File

@@ -71,7 +71,6 @@ def parseArgs():
if __name__ == "__main__":
args = parseArgs()
db = getDBConnection(args.db_uri)

1
util/gem5art/run/gem5art/run.py
View File

@@ -672,7 +672,6 @@ def getRunsByNameLike(
def getRerunnableRunsByNameLike(
db: ArtifactDB, name: str, fs_only: bool = False, limit: int = 0
) -> Iterable[gem5Run]:
"""Returns a generator of gem5Run objects having rerunnable as true
and the object "name" containing the name parameter as a substring. The
parameter is case sensitive.

1
util/gem5img.py
View File

@@ -65,6 +65,7 @@ env["PATH"] += ":/sbin:/usr/sbin"
# Whether to print debug output.
debug = False
# Figure out cylinders, heads and sectors from a size in blocks.
def chsFromSize(sizeInBlocks):
if sizeInBlocks >= MaxLBABlocks:

4
util/logroll.py
View File

@@ -214,7 +214,6 @@ class TestLogroll(unittest.TestCase):
) as mock_signal, unittest.mock.patch(
__name__ + ".dump_lines", new_callable=CopyingMock
) as mock_dump_lines:
signal_dict = self.mock_signal_dict(mock_signal)
main(
@@ -237,7 +236,6 @@ class TestLogroll(unittest.TestCase):
) as mock_signal, unittest.mock.patch(
__name__ + ".dump_lines", new_callable=CopyingMock
) as mock_dump_lines:
signal_dict = self.mock_signal_dict(mock_signal)
with self.assertRaises(SystemExit):
@@ -258,7 +256,6 @@ class TestLogroll(unittest.TestCase):
) as mock_signal, unittest.mock.patch(
__name__ + ".dump_lines", new_callable=CopyingMock
) as mock_dump_lines:
signal_dict = self.mock_signal_dict(mock_signal)
main(
@@ -283,7 +280,6 @@ class TestLogroll(unittest.TestCase):
) as mock_signal, unittest.mock.patch(
__name__ + ".dump_lines", new_callable=CopyingMock
) as mock_dump_lines:
signal_dict = self.mock_signal_dict(mock_signal)
with self.assertRaises(SystemExit):

1
util/maint/lib/maintainers.py
View File

@@ -118,7 +118,6 @@ class Maintainers(object):
def from_file(
cls, path_or_file: Optional[PathOrFile] = None
) -> "Maintainers":
return cls(Maintainers._load_maintainers_file(path_or_file))
@classmethod

2
util/on-chip-network-power-area.py
View File

@@ -55,6 +55,7 @@ os.chdir("../../../")
sys.path.append("build/ext/dsent")
import dsent
# Parse gem5 config.ini file for the configuration parameters related to
# the on-chip network.
def parseConfig(config_file):
@@ -182,7 +183,6 @@ def parseStats(
buffers_per_control_vc,
ni_flit_size_bits,
):
# Open the stats.txt file and parse it to for the required numbers
# and the number of routers.
try:

2
util/plot_dram/PlotPowerStates.py
View File

@@ -150,7 +150,6 @@ def plotLowPStates(
for delay in delayValues:
for bank_util in bankUtilValues:
for seq_bytes in seqBytesValues:
for line in stats_file:
if "Begin" in line:
break
@@ -261,7 +260,6 @@ def plotStackedStates(delay, states_list, bottom_state, plot_name, ylabel_str):
ind = np.arange(N)
for sub_idx, bank_util in enumerate(bankUtilValues):
l_states = {}
p_states = {}

4
util/plot_dram/dram_lat_mem_rd_plot.py
View File

@@ -46,11 +46,11 @@ except ImportError:
import sys
import re
# This script is intended to post process and plot the output from
# running configs/dram/lat_mem_rd.py, as such it parses the simout.txt and
# stats.txt to get the relevant data points.
def main():
if len(sys.argv) != 2:
print("Usage: ", sys.argv[0], "<simout directory>")
exit(-1)
@@ -122,7 +122,7 @@ def main():
)
exit(-1)
for (r, l) in zip(ranges, final_rd_lat):
for r, l in zip(ranges, final_rd_lat):
print(r, round(l, 2))
# lazy version to check if an integer is a power of two

2
util/plot_dram/dram_sweep_plot.py
View File

@@ -47,12 +47,12 @@ except ImportError:
import sys
import re
# Determine the parameters of the sweep from the simout output, and
# then parse the stats and plot the 3D surface corresponding to the
# different combinations of parallel banks, and stride size, as
# generated by the config/dram/sweep.py script
def main():
if len(sys.argv) != 3:
print("Usage: ", sys.argv[0], "-u|p|e <simout directory>")
exit(-1)

2
util/plot_dram/lowp_dram_sweep_plot.py
View File

@@ -140,7 +140,6 @@ def wrapForGraphic(filename, width="1.0"):
def startDocText(outfile):
start_stuff = """
\\documentclass[a4paper,landscape,twocolumn]{article}
@@ -152,7 +151,6 @@ def startDocText(outfile):
def endDocText(outfile):
end_stuff = """
\\end{document}

2
util/streamline/m5stats2streamline.py
View File

@@ -143,6 +143,7 @@ num_events = args.num_events
start_tick = -1
end_tick = -1
# Parse gem5 config.ini file to determine some system configurations.
# Number of CPUs, L2s, etc.
def parseConfig(config_file):
@@ -814,7 +815,6 @@ def writeXmlFile(xml, filename):
# StatsEntry that contains individual statistics
class StatsEntry(object):
def __init__(self, name, group, group_index, per_cpu, key):
# Full name of statistics
self.name = name

1
util/systemc/systemc_within_gem5/systemc_gem5_tlm/SystemC_Example.py
View File

@@ -31,6 +31,7 @@ from m5.proxy import *
from m5.objects.SystemC import SystemC_ScModule
from m5.objects.Tlm import TlmTargetSocket
# This class is a subclass of sc_module, and all the special magic which makes
# that work is handled in the base classes.
class TLM_Target(SystemC_ScModule):

1
util/systemc/systemc_within_gem5/systemc_simple_object/SystemC_Example.py
View File

@@ -28,6 +28,7 @@ from m5.SimObject import SimObject
from m5.objects.SystemC import SystemC_ScModule
# This class is a subclass of sc_module, and all the special magic which makes
# that work is handled in the base classes.
class SystemC_Printer(SystemC_ScModule):