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misc: Run pre-commit autoupdate (#419)

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1. Runs `pre-commit autoupdate`.
2. Runs `pre-commit run --all-files`.
3. Adds (2.) to ".git-blame-ignore-rev".
This commit is contained in:
Bobby R. Bruce
2023-10-10 21:41:33 -07:00
committed by GitHub
parent d559c24ac2 1502f7c09f
commit 3f5d7d647a
185 changed files with 125 additions and 177 deletions
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5
src/python/gem5/components/boards/arm_board.py
View File

@@ -88,7 +88,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
platform: VExpress_GEM5_Base = VExpress_GEM5_Foundation(),
release: ArmRelease = ArmDefaultRelease(),
) -> None:
# The platform and the clk has to be set before calling the super class
self._platform = platform
self._clk_freq = clk_freq
@@ -117,7 +116,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
@overrides(AbstractBoard)
def _setup_board(self) -> None:
# This board is expected to run full-system simulation.
# Loading ArmFsLinux() from `src/arch/arm/ArmFsWorkload.py`
self.workload = ArmFsLinux()
@@ -213,7 +211,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
# created. The IO device has to be attached first. This is done in the
# realview class.
if self.get_cache_hierarchy().is_ruby():
# All the on-chip devices are attached in this method.
self.realview.attachOnChipIO(
self.iobus,
@@ -359,7 +356,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
@overrides(KernelDiskWorkload)
def _add_disk_to_board(self, disk_image: AbstractResource):
self._image = CowDiskImage(
child=RawDiskImage(
read_only=True, image_file=disk_image.get_local_path()
@@ -379,7 +375,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
@overrides(KernelDiskWorkload)
def get_default_kernel_args(self) -> List[str]:
# The default kernel string is taken from the devices.py file.
return [
"console=ttyAMA0",

2
src/python/gem5/components/boards/experimental/lupv_board.py
View File

@@ -90,7 +90,6 @@ class LupvBoard(AbstractSystemBoard, KernelDiskWorkload):
memory: AbstractMemorySystem,
cache_hierarchy: AbstractCacheHierarchy,
) -> None:
if cache_hierarchy.is_ruby():
raise EnvironmentError("RiscvBoard is not compatible with Ruby")
@@ -105,7 +104,6 @@ class LupvBoard(AbstractSystemBoard, KernelDiskWorkload):
@overrides(AbstractSystemBoard)
def _setup_board(self) -> None:
self.workload = RiscvLinux()
# Initialize all the devices that we want to use on this board

1
src/python/gem5/components/boards/x86_board.py
View File

@@ -202,7 +202,6 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload):
base_entries.append(pci_dev4_inta)
def assignISAInt(irq, apicPin):
assign_8259_to_apic = X86IntelMPIOIntAssignment(
interrupt_type="ExtInt",
polarity="ConformPolarity",

1
src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py
View File

@@ -75,7 +75,6 @@ class PrivateL1CacheHierarchy(AbstractRubyCacheHierarchy):
@overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None:
requires(coherence_protocol_required=CoherenceProtocol.CHI)
self.ruby_system = RubySystem()

2
src/python/gem5/components/cachehierarchies/classic/no_cache.py
View File

@@ -97,12 +97,10 @@ class NoCache(AbstractClassicCacheHierarchy):
@overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None:
if board.has_coherent_io():
self._setup_coherent_io_bridge(board)
for core in board.get_processor().get_cores():
core.connect_icache(self.membus.cpu_side_ports)
core.connect_dcache(self.membus.cpu_side_ports)
core.connect_walker_ports(

2
src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py
View File

@@ -86,7 +86,6 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
@overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None:
# Set up the system port for functional access from the simulator.
board.connect_system_port(self.membus.cpu_side_ports)
@@ -117,7 +116,6 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
self._setup_io_cache(board)
for i, cpu in enumerate(board.get_processor().get_cores()):
cpu.connect_icache(self.l1icaches[i].cpu_side)
cpu.connect_dcache(self.l1dcaches[i].cpu_side)

2
src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
View File

@@ -111,7 +111,6 @@ class PrivateL1PrivateL2CacheHierarchy(
@overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None:
# Set up the system port for functional access from the simulator.
board.connect_system_port(self.membus.cpu_side_ports)
@@ -148,7 +147,6 @@ class PrivateL1PrivateL2CacheHierarchy(
self._setup_io_cache(board)
for i, cpu in enumerate(board.get_processor().get_cores()):
cpu.connect_icache(self.l1icaches[i].cpu_side)
cpu.connect_dcache(self.l1dcaches[i].cpu_side)

2
src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py
View File

@@ -107,7 +107,6 @@ class PrivateL1SharedL2CacheHierarchy(
@overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None:
# Set up the system port for functional access from the simulator.
board.connect_system_port(self.membus.cpu_side_ports)
@@ -143,7 +142,6 @@ class PrivateL1SharedL2CacheHierarchy(
self._setup_io_cache(board)
for i, cpu in enumerate(board.get_processor().get_cores()):
cpu.connect_icache(self.l1icaches[i].cpu_side)
cpu.connect_dcache(self.l1dcaches[i].cpu_side)

1
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py
View File

@@ -30,7 +30,6 @@ from m5.objects import Directory_Controller
class AbstractDirectory(Directory_Controller):
_version = 0
@classmethod

1
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py
View File

@@ -30,7 +30,6 @@ from m5.objects import DMA_Controller
class AbstractDMAController(DMA_Controller):
_version = 0
@classmethod

1
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py
View File

@@ -35,7 +35,6 @@ import math
class AbstractL1Cache(L1Cache_Controller):
_version = 0
@classmethod

1
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py
View File

@@ -30,7 +30,6 @@ from m5.objects import L2Cache_Controller
class AbstractL2Cache(L2Cache_Controller):
_version = 0
@classmethod

1
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/directory.py
View File

@@ -32,7 +32,6 @@ from m5.objects import MessageBuffer, RubyDirectoryMemory
class Directory(AbstractDirectory):
def __init__(self, network, cache_line_size, mem_range, port):
super().__init__(network, cache_line_size)
self.addr_ranges = [mem_range]
self.directory = RubyDirectoryMemory()

2
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py
View File

@@ -39,10 +39,10 @@ from m5.objects import (
import math
# L0Cache_Controller is the ruby backend's terminology corresponding to
# L1 cache in stdlib terms.
class L1Cache(L0Cache_Controller):
_version = 0
@classmethod

2
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py
View File

@@ -38,10 +38,10 @@ from m5.objects import (
import math
# L1Cache_Controller is ruby backend's terminology corresponding to
# L2Cache in stdlib's terms
class L2Cache(L1Cache_Controller):
_version = 0
@classmethod

2
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py
View File

@@ -28,10 +28,10 @@ from m5.objects import MessageBuffer, RubyCache, L2Cache_Controller
import math
# L2Cache_Controller is ruby backend's terminology corresponding to
# L3 cache in stdlib.
class L3Cache(L2Cache_Controller):
_version = 0
@classmethod

1
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py
View File

@@ -32,7 +32,6 @@ from m5.objects import MessageBuffer, RubyDirectoryMemory
class Directory(AbstractDirectory):
def __init__(self, network, cache_line_size, mem_range, port):
super().__init__(network, cache_line_size)
self.addr_ranges = [mem_range]
self.directory = RubyDirectoryMemory()

1
src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py
View File

@@ -37,7 +37,6 @@ class Directory(AbstractDirectory):
"""
def __init__(self, network, cache_line_size, mem_range, port):
super().__init__(network, cache_line_size)
self.addr_ranges = [mem_range]
self.directory = RubyDirectoryMemory()

2
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi.py
View File

@@ -45,6 +45,7 @@ from .core_complex import CoreComplex
from .octopi_network import OctopiNetwork
from .ruby_network_components import RubyRouter, RubyExtLink, RubyIntLink
# CoreComplex sub-systems own the L1, L2, L3 controllers
# OctopiCache owns the directory controllers
# RubySystem owns the DMA Controllers
@@ -85,7 +86,6 @@ class OctopiCache(
self._is_fullsystem = is_fullsystem
def incorporate_cache(self, board: AbstractBoard) -> None:
requires(
coherence_protocol_required=CoherenceProtocol.MESI_THREE_LEVEL
)

1
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi_network.py
View File

@@ -32,6 +32,7 @@ from .ruby_network_components import (
RubyIntLink,
)
# . The Network owns all routers, all int links and all ext links that are not in CCD's.
# . The CCD subsystems are not of type RubyNetwork, so we need to copy the references of
# routers and links to OctopiNetwork._routers, ._int_links, and ._ext_links; which will

1
src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py
View File

@@ -80,7 +80,6 @@ class MESIThreeLevelCacheHierarchy(
self._num_l3_banks = num_l3_banks
def incorporate_cache(self, board: AbstractBoard) -> None:
requires(
coherence_protocol_required=CoherenceProtocol.MESI_THREE_LEVEL
)

1
src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py
View File

@@ -76,7 +76,6 @@ class MESITwoLevelCacheHierarchy(
self._num_l2_banks = num_l2_banks
def incorporate_cache(self, board: AbstractBoard) -> None:
requires(coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL)
cache_line_size = board.get_cache_line_size()

1
src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py
View File

@@ -58,7 +58,6 @@ class MIExampleCacheHierarchy(AbstractRubyCacheHierarchy):
@overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None:
requires(coherence_protocol_required=CoherenceProtocol.MI_EXAMPLE)
self.ruby_system = RubySystem()

1
src/python/gem5/components/memory/dram_interfaces/hbm.py
View File

@@ -201,7 +201,6 @@ class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
# on HBM gen2 specifications. 4H stack, 8Gb per die and total capacity
# of 4GiB.
class HBM_2000_4H_1x64(DRAMInterface):
# 64-bit interface for a single pseudo channel
device_bus_width = 64

1
src/python/gem5/components/memory/hbm.py
View File

@@ -137,7 +137,6 @@ class HighBandwidthMemory(ChanneledMemory):
@overrides(ChanneledMemory)
def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
intlv_bits = log(self._num_channels, 2)
mask_list = []

3
src/python/gem5/components/processors/base_cpu_core.py
View File

@@ -93,7 +93,6 @@ class BaseCPUCore(AbstractCore):
@overrides(AbstractCore)
def is_kvm_core(self) -> bool:
try:
from m5.objects import BaseKvmCPU
@@ -118,7 +117,6 @@ class BaseCPUCore(AbstractCore):
@overrides(AbstractCore)
def connect_walker_ports(self, port1: Port, port2: Port) -> None:
if self.get_isa() == ISA.ARM:
# Unlike X86 and RISCV MMU, the ARM MMU has two L1 TLB walker ports
# named `walker` and `stage2_walker` for both data and instruction.
# The gem5 standard library currently supports one TLB walker port
@@ -144,7 +142,6 @@ class BaseCPUCore(AbstractCore):
interrupt_requestor: Optional[Port] = None,
interrupt_responce: Optional[Port] = None,
) -> None:
# TODO: This model assumes that we will only create an interrupt
# controller as we require it. Not sure how true this is in all cases.
self.core.createInterruptController()

1
src/python/gem5/components/processors/base_cpu_processor.py
View File

@@ -71,7 +71,6 @@ class BaseCPUProcessor(AbstractProcessor):
@overrides(AbstractProcessor)
def incorporate_processor(self, board: AbstractBoard) -> None:
if any(core.is_kvm_core() for core in self.get_cores()):
board.kvm_vm = self.kvm_vm
# To get the KVM CPUs to run on different host CPUs

1
src/python/gem5/components/processors/simple_core.py
View File

@@ -44,7 +44,6 @@ class SimpleCore(BaseCPUCore):
def __init__(
self, cpu_type: CPUTypes, core_id: int, isa: Optional[ISA] = None
):
# If the ISA is not specified, we infer it via the `get_runtime_isa`
# function.
if isa:

3
src/python/gem5/components/processors/switchable_processor.py
View File

@@ -52,7 +52,6 @@ class SwitchableProcessor(AbstractProcessor):
switchable_cores: Dict[str, List[SimpleCore]],
starting_cores: str,
) -> None:
if starting_cores not in switchable_cores.keys():
raise AssertionError(
f"Key {starting_cores} cannot be found in the "
@@ -85,7 +84,6 @@ class SwitchableProcessor(AbstractProcessor):
@overrides(AbstractProcessor)
def incorporate_processor(self, board: AbstractBoard) -> None:
# This is a bit of a hack. The `m5.switchCpus` function, used in the
# "switch_to_processor" function, requires the System simobject as an
# argument. We therefore need to store the board when incorporating the
@@ -119,7 +117,6 @@ class SwitchableProcessor(AbstractProcessor):
yield core
def switch_to_processor(self, switchable_core_key: str):
# Run various checks.
if not hasattr(self, "_board"):
raise AssertionError("The processor has not been incorporated.")

2
src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py
View File

@@ -97,7 +97,6 @@ class RISCVMatchedCacheHierarchy(
@overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None:
# Set up the system port for functional access from the simulator.
board.connect_system_port(self.membus.cpu_side_ports)
@@ -135,7 +134,6 @@ class RISCVMatchedCacheHierarchy(
self._setup_io_cache(board)
for i, cpu in enumerate(board.get_processor().get_cores()):
cpu.connect_icache(self.l1icaches[i].cpu_side)
cpu.connect_dcache(self.l1dcaches[i].cpu_side)

1
src/python/gem5/resources/client_api/client_wrapper.py
View File

@@ -64,7 +64,6 @@ class ClientWrapper:
clients: Optional[List[str]] = None,
gem5_version: Optional[str] = core.gem5Version,
) -> Dict[str, List[str]]:
clients_to_search = (
list(self.clients.keys()) if clients is None else clients
)

2
src/python/gem5/resources/downloader.py
View File

@@ -369,7 +369,6 @@ def get_resource(
with tarfile.open(download_dest) as f:
def is_within_directory(directory, target):
abs_directory = os.path.abspath(directory)
abs_target = os.path.abspath(target)
@@ -380,7 +379,6 @@ def get_resource(
def safe_extract(
tar, path=".", members=None, *, numeric_owner=False
):
for member in tar.getmembers():
member_path = os.path.join(path, member.name)
if not is_within_directory(path, member_path):

1
src/python/gem5/resources/looppoint.py
View File

@@ -491,7 +491,6 @@ class LooppointJsonLoader(Looppoint):
with open(_path) as file:
json_contents = json.load(file)
for rid in json_contents:
start_pc = int(json_contents[rid]["simulation"]["start"]["pc"])
start_globl = int(
json_contents[rid]["simulation"]["start"]["global"]

1
src/python/gem5/resources/resource.py
View File

@@ -863,7 +863,6 @@ def obtain_resource(
# If the "url" field is specified, the resoruce must be downloaded.
if "url" in resource_json and resource_json["url"]:
# If the `to_path` parameter is set, we use that as the path to which
# the resource is to be downloaded. Otherwise, default to the
# `resource_directory` parameter plus the resource ID.

6
src/python/gem5/simulate/simulator.py
View File

@@ -464,7 +464,7 @@ class Simulator:
"""
start = 0
to_return = []
for (exit_event, tick) in self._tick_stopwatch:
for exit_event, tick in self._tick_stopwatch:
if exit_event == ExitEvent.WORKBEGIN:
start = tick
elif exit_event == ExitEvent.WORKEND:
@@ -480,7 +480,6 @@ class Simulator:
"""
if not self._instantiated:
# Before anything else we run the AbstractBoard's
# `_pre_instantiate` function.
self._board._pre_instantiate()
@@ -557,7 +556,6 @@ class Simulator:
# This while loop will continue until an a generator yields True.
while True:
self._last_exit_event = m5.simulate(max_ticks)
# Translate the exit event cause to the exit event enum.
@@ -584,7 +582,7 @@ class Simulator:
# If the user has specified their own generator for this exit
# event, use it.
exit_on_completion = next(self._on_exit_event[exit_enum])
except (StopIteration):
except StopIteration:
# If the user's generator has ended, throw a warning and use
# the default generator for this exit event.
warn(

1
src/python/gem5/utils/multiprocessing/context.py
View File

@@ -33,6 +33,7 @@ multiprocessing module (i.e., cpython/Lib/multiprocessing/).
from multiprocessing import context, process
from multiprocessing.context import DefaultContext
# The `_start_method` must be `None` for the `Spawn_gem5Process` class.
# Otherwise, in `_bootstrap` in the `BaseProcess` it will try to force the
# `_start_method` to be gem5-specific, which the `multiprocessing` module

1
src/python/gem5/utils/progress_bar.py
View File

@@ -55,6 +55,7 @@ except ImportError:
tqdm = FakeTQDM()
_have_tqdm = False
# Hook for the progress bar
def progress_hook(t):
if not _have_tqdm:

4
src/python/m5/SimObject.py
View File

@@ -1252,7 +1252,7 @@ class SimObject(object, metaclass=MetaSimObject):
# The order of the dict is implementation dependent, so sort
# it based on the key (name) to ensure the order is the same
# on all hosts
for (name, child) in sorted(self._children.items()):
for name, child in sorted(self._children.items()):
for obj in child.descendants():
yield obj
@@ -1275,7 +1275,7 @@ class SimObject(object, metaclass=MetaSimObject):
def connectPorts(self):
# Sort the ports based on their attribute name to ensure the
# order is the same on all hosts
for (attr, portRef) in sorted(self._port_refs.items()):
for attr, portRef in sorted(self._port_refs.items()):
portRef.ccConnect()
# Default function for generating the device structure.

7
src/python/m5/params.py
View File

@@ -453,6 +453,7 @@ VectorParam = ParamFactory(VectorParamDesc)
#
#####################################################################
# String-valued parameter. Just mixin the ParamValue class with the
# built-in str class.
class String(ParamValue, str):
@@ -1524,10 +1525,11 @@ class Time(ParamValue):
# derive the new type from the appropriate base class on the fly.
allEnums = {}
# Metaclass for Enum types
class MetaEnum(MetaParamValue):
def __new__(mcls, name, bases, dict):
cls = super().__new__(mcls, name, bases, dict)
allEnums[name] = cls
return cls
@@ -1963,6 +1965,7 @@ class MemoryBandwidth(float, ParamValue):
# "Constants"... handy aliases for various values.
#
# Special class for NULL pointers. Note the special check in
# make_param_value() above that lets these be assigned where a
# SimObject is required.
@@ -2030,6 +2033,7 @@ AllMemory = AddrRange(0, MaxAddr)
#
#####################################################################
# Port reference: encapsulates a reference to a particular port on a
# particular SimObject.
class PortRef(object):
@@ -2371,6 +2375,7 @@ SlavePort = ResponsePort
VectorMasterPort = VectorRequestPort
VectorSlavePort = VectorResponsePort
# 'Fake' ParamDesc for Port references to assign to the _pdesc slot of
# proxy objects (via set_param_desc()) so that proxy error messages
# make sense.

1
src/python/m5/simulate.py
View File

@@ -65,6 +65,7 @@ _drain_manager = _m5.drain.DrainManager.instance()
_instantiated = False # Has m5.instantiate() been called?
# The final call to instantiate the SimObject graph and initialize the
# system.
def instantiate(ckpt_dir=None):

1
src/python/m5/ticks.py
View File

@@ -29,6 +29,7 @@ import decimal
import sys
from m5.util import warn
# fix the global frequency
def fixGlobalFrequency():
import _m5.core

1
src/python/m5/util/__init__.py
View File

@@ -48,6 +48,7 @@ from . import convert
from .attrdict import attrdict, multiattrdict, optiondict
from .multidict import multidict
# panic() should be called when something happens that should never
# ever happen regardless of what the user does (i.e., an acutal m5
# bug).

1
src/python/m5/util/terminal_formatter.py
View File

@@ -45,7 +45,6 @@ class TerminalFormatter:
return w, h
def __get_paragraphs(self, text, flatten=False):
"""
This function takes a text and returns a list of constituent
paragraphs, defining a paragraph as a block of text separated from