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arch-riscv: Remove static parts of AMOs out of ISA

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This patch removes the static parts of the RISC-V atomic memory
instructions out of the ISA generated code and into arch/riscv/insts. It
also makes the LR and SC instructions subclasses of MemInst from
arch/riscv/insts/mem.hh.

Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
Reviewed-on: https://gem5-review.googlesource.com/6025
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
This commit is contained in:
Alec Roelke
2017-11-10 12:23:43 -05:00
parent 719ddf73af
commit 3f31abfbc8
5 changed files with 168 additions and 97 deletions
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1
src/arch/riscv/insts/SConscript
View File

@@ -1,6 +1,7 @@
Import('*')
if env['TARGET_ISA'] == 'riscv':
Source('amo.cc')
Source('mem.cc')
Source('standard.cc')
Source('static_inst.cc')

83
src/arch/riscv/insts/amo.cc Normal file
View File

@@ -0,0 +1,83 @@
/*
* Copyright (c) 2015 RISC-V Foundation
* Copyright (c) 2017 The University of Virginia
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Alec Roelke
*/
#include "arch/riscv/insts/amo.hh"
#include <sstream>
#include <string>
#include "arch/riscv/utility.hh"
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"
using namespace std;
namespace RiscvISA
{
string LoadReserved::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
<< registerName(_srcRegIdx[0]) << ')';
return ss.str();
}
string StoreCond::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
<< registerName(_srcRegIdx[1]) << ", ("
<< registerName(_srcRegIdx[0]) << ')';
return ss.str();
}
string AtomicMemOp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
<< registerName(_srcRegIdx[1]) << ", ("
<< registerName(_srcRegIdx[0]) << ')';
return ss.str();
}
string AtomicMemOpMicro::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
stringstream ss;
ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
return ss.str();
}
}

83
src/arch/riscv/insts/amo.hh Normal file
View File

@@ -0,0 +1,83 @@
/*
* Copyright (c) 2015 RISC-V Foundation
* Copyright (c) 2017 The University of Virginia
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Alec Roelke
*/
#ifndef __ARCH_RISCV_INSTS_AMO_HH__
#define __ARCH_RISCV_INSTS_AMO_HH__
#include <string>
#include "arch/riscv/insts/mem.hh"
#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"
namespace RiscvISA
{
class LoadReserved : public MemInst
{
protected:
using MemInst::MemInst;
std::string generateDisassembly(
Addr pc, const SymbolTable *symtab) const override;
};
class StoreCond : public MemInst
{
protected:
using MemInst::MemInst;
std::string generateDisassembly(
Addr pc, const SymbolTable *symtab) const override;
};
class AtomicMemOp : public RiscvMacroInst
{
protected:
using RiscvMacroInst::RiscvMacroInst;
std::string generateDisassembly(
Addr pc, const SymbolTable *symtab) const override;
};
class AtomicMemOpMicro : public RiscvMicroInst
{
protected:
Request::Flags memAccessFlags;
using RiscvMicroInst::RiscvMicroInst;
std::string generateDisassembly(
Addr pc, const SymbolTable *symtab) const override;
};
}
#endif // __ARCH_RISCV_INSTS_AMO_HH__

97
src/arch/riscv/isa/formats/amo.isa
View File

@@ -33,103 +33,6 @@
//
// Atomic memory operation instructions
//
output header {{
class LoadReserved : public RiscvStaticInst
{
protected:
Request::Flags memAccessFlags;
LoadReserved(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass)
{}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class StoreCond : public RiscvStaticInst
{
protected:
Request::Flags memAccessFlags;
StoreCond(const char* mnem, ExtMachInst _machInst, OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass)
{}
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class AtomicMemOp : public RiscvMacroInst
{
protected:
/// Constructor
// Each AtomicMemOp has a load and a store phase
AtomicMemOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
: RiscvMacroInst(mnem, _machInst, __opClass)
{}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
class AtomicMemOpMicro : public RiscvMicroInst
{
protected:
/// Memory request flags. See mem/request.hh.
Request::Flags memAccessFlags;
/// Constructor
AtomicMemOpMicro(const char *mnem, ExtMachInst _machInst,
OpClass __opClass)
: RiscvMicroInst(mnem, _machInst, __opClass)
{}
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
};
}};
output decoder {{
std::string LoadReserved::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ("
<< registerName(_srcRegIdx[0]) << ')';
return ss.str();
}
std::string StoreCond::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
<< registerName(_srcRegIdx[1]) << ", ("
<< registerName(_srcRegIdx[0]) << ')';
return ss.str();
}
std::string AtomicMemOp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", "
<< registerName(_srcRegIdx[1]) << ", ("
<< registerName(_srcRegIdx[0]) << ')';
return ss.str();
}
std::string AtomicMemOpMicro::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream ss;
ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
return ss.str();
}
}};
def template AtomicMemOpDeclare {{
/**
* Static instruction class for an AtomicMemOp operation

1
src/arch/riscv/isa/includes.isa
View File

@@ -42,6 +42,7 @@ output header {{
#include <tuple>
#include <vector>
#include "arch/riscv/insts/amo.hh"
#include "arch/riscv/insts/mem.hh"
#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"