ARM: add support for TEEHBR access

Thumb2 ARM kernels may access the TEEHBR via thumbee_notifier
in arch/arm/kernel/thumbee.c.  The Linux kernel code just seems
to be saving and restoring the register.  This patch adds support
for the TEEHBR cp14 register.  Note, this may be a special case
when restoring from an image that was run on a system that
supports ThumbEE.

src/arch/arm/miscregs.cc

@@ -63,9 +63,32 @@ decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
                 return NUM_MISCREGS;
             }
           default:
+            warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+                 crn, opc1, crm, opc2);
+            return NUM_MISCREGS;
+        }
+      case 1:
+        switch (opc1) {
+          case 6:
+            switch (crm) {
+              case 0:
+                switch (opc2) {
+                  case 0:
+                    return MISCREG_TEEHBR;
+                  default:
+                    warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+                         crn, opc1, crm, opc2);
+                    return NUM_MISCREGS;
+                }
+              default:
                 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
                      crn, opc1, crm, opc2);
                 return NUM_MISCREGS;
+            }
+          default:
+            warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+                 crn, opc1, crm, opc2);
+            return NUM_MISCREGS;
         }
       default:
         warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",

src/arch/arm/miscregs.hh

@@ -121,6 +121,7 @@ namespace ArmISA
         MISCREG_DBGDEVID2,
         MISCREG_DBGDEVID1,
         MISCREG_DBGDEVID,
+        MISCREG_TEEHBR,
 
         // CP15 registers
         MISCREG_CP15_START,
@@ -288,6 +289,7 @@ namespace ArmISA
         "DBGDEVID2",
         "DBGDEVID1",
         "DBGDEVID",
+        "TEEHBR",
         "sctlr", "dccisw", "dccimvac", "dccmvac",
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
         "cp15isb", "cp15dsb", "cp15dmb", "cpacr",

src/sim/serialize.hh

@@ -57,7 +57,7 @@ class SimObject;
  * SimObject shouldn't cause the version number to increase, only changes to
  * existing objects such as serializing/unserializing more state, changing sizes
  * of serialized arrays, etc. */
-static const uint64_t gem5CheckpointVersion = 0x0000000000000007;
+static const uint64_t gem5CheckpointVersion = 0x0000000000000008;
 
 template <class T>
 void paramOut(std::ostream &os, const std::string &name, const T &param);

util/cpt_upgrader.py

@@ -217,6 +217,18 @@ def from_6(cpt):
         if cpt.has_option(sec, "curSector"):
             cpt.set(sec, "dmaAborted", "false")
 
+# Version 8 of the checkpoint adds an ARM MISCREG
+def from_7(cpt):
+    if cpt.get('root','isa') == 'arm':
+        for sec in cpt.sections():
+            import re
+            # Search for all ISA sections
+            if re.search('.*sys.*\.cpu.*\.isa', sec):
+                mr = cpt.get(sec, 'miscRegs').split()
+                # Add dummy value for MISCREG_TEEHBR
+                mr.insert(51,0);
+                cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
+
 
 migrations = []
 migrations.append(from_0)
@@ -226,6 +238,7 @@ migrations.append(from_3)
 migrations.append(from_4)
 migrations.append(from_5)
 migrations.append(from_6)
+migrations.append(from_7)
 
 verbose_print = False