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Merge zizzer:/bk/m5

Browse Source 
into  zeep.eecs.umich.edu:/z/saidi/work/m5

--HG--
extra : convert_revision : 3cc23080d19cc464a8ba7c1c93b6e5d45af7d463
This commit is contained in:
Ali Saidi
2005-11-02 14:56:18 -05:00
parent 0523736b96 a0829a7780
commit 3b66cb49ec
19 changed files with 936 additions and 845 deletions
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3
python/m5/objects/Ethernet.py
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@@ -84,6 +84,7 @@ class EtherDevBase(PciDevice):
rx_filter = Param.Bool(True, "Enable Receive Filter")
intr_delay = Param.Latency('10us', "Interrupt Propagation Delay")
dedicated = Param.Bool(False, "dedicate a kernel thread to the driver")
class NSGigE(EtherDevBase):
type = 'NSGigE'
@@ -91,7 +92,6 @@ class NSGigE(EtherDevBase):
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dedicated = Param.Bool(False, "dedicate a kernel thread to the driver")
class NSGigEInt(EtherInt):
type = 'NSGigEInt'
@@ -102,6 +102,7 @@ class Sinic(EtherDevBase):
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
tx_max_copy = Param.MemorySize('16kB', "tx max copy")
rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold")
tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold")