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tests: Update tests to use ALL/gem5.opt compilation

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Where possible the gem5 tests have been updated to use the
build/ALL/gem5.opt compilation.

If a quick test requied a specific a ISA/protocol compilation they
were moved to the long/nightly set. This means all the quick/kokoro
tests are run with the build/ALL/gem5.opt compilation.

The learning_gem5 tests have been updated to use ALL/gem5.opt.

The equivilant examples on the website have been updated via:
https://gem5-review.googlesource.com/c/public/gem5-website/+/63336

Change-Id: I533689ad6848233867bdba9e9a43bb5840ed65c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63374
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Bobby R. Bruce
2022-09-08 18:19:27 -07:00
committed by Bobby Bruce
parent 2429a6dd58
commit 3b0cb574f5
70 changed files with 455 additions and 225 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
configs/example/gem5_library/arm-ubuntu-boot-exit.py
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@@ -76,7 +76,7 @@ memory = DualChannelDDR4_2400(size="2GB")
# Here we setup the processor. We use a simple TIMING processor. The config
# script was also tested with ATOMIC processor.
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=2)
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=2, isa=ISA.ARM)
# The ArmBoard requires a `release` to be specified. This adds all the
# extensions or features to the system. We are setting this to Armv8

78
configs/learning_gem5/part1/simple-arm.py Normal file
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@@ -0,0 +1,78 @@
# Copyright (c) 2015 Jason Power
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
"""
This is the ARM equivalent to `simple.py` (which is designed to run using the
X86 ISA). More detailed documentation can be found in `simple.py`.
"""
import m5
from m5.objects import *
system = System()
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = "1GHz"
system.clk_domain.voltage_domain = VoltageDomain()
system.mem_mode = "timing"
system.mem_ranges = [AddrRange("512MB")]
system.cpu = ArmTimingSimpleCPU()
system.membus = SystemXBar()
system.cpu.icache_port = system.membus.cpu_side_ports
system.cpu.dcache_port = system.membus.cpu_side_ports
system.cpu.createInterruptController()
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.mem_side_ports
system.system_port = system.membus.cpu_side_ports
thispath = os.path.dirname(os.path.realpath(__file__))
binary = os.path.join(
thispath,
"../../../",
"tests/test-progs/hello/bin/arm/linux/hello",
)
system.workload = SEWorkload.init_compatible(binary)
process = Process()
process.cmd = [binary]
system.cpu.workload = process
system.cpu.createThreads()
root = Root(full_system=False, system=system)
m5.instantiate()
print("Beginning simulation!")
exit_event = m5.simulate()
print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause()))

78
configs/learning_gem5/part1/simple-riscv.py Normal file
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@@ -0,0 +1,78 @@
# Copyright (c) 2015 Jason Power
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
"""
This is the RISCV equivalent to `simple.py` (which is designed to run using the
X86 ISA). More detailed documentation can be found in `simple.py`.
"""
import m5
from m5.objects import *
system = System()
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = "1GHz"
system.clk_domain.voltage_domain = VoltageDomain()
system.mem_mode = "timing"
system.mem_ranges = [AddrRange("512MB")]
system.cpu = RiscvTimingSimpleCPU()
system.membus = SystemXBar()
system.cpu.icache_port = system.membus.cpu_side_ports
system.cpu.dcache_port = system.membus.cpu_side_ports
system.cpu.createInterruptController()
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.mem_side_ports
system.system_port = system.membus.cpu_side_ports
thispath = os.path.dirname(os.path.realpath(__file__))
binary = os.path.join(
thispath,
"../../../",
"tests/test-progs/hello/bin/riscv/linux/hello",
)
system.workload = SEWorkload.init_compatible(binary)
process = Process()
process.cmd = [binary]
system.cpu.workload = process
system.cpu.createThreads()
root = Root(full_system=False, system=system)
m5.instantiate()
print("Beginning simulation!")
exit_event = m5.simulate()
print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause()))

35
configs/learning_gem5/part1/simple.py
View File

@@ -1,4 +1,3 @@
# -*- coding: utf-8 -*-
# Copyright (c) 2015 Jason Power
# All rights reserved.
#
@@ -33,6 +32,10 @@ learning_gem5 book for more information about this script.
IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
also needs to be updated. For now, email Jason <power.jg@gmail.com>
This script uses the X86 ISA. `simple-arm.py` and `simple-riscv.py` may be
referenced as examples of scripts which utilize the ARM and RISC-V ISAs
respectively.
"""
# import the m5 (gem5) library created when gem5 is built
@@ -40,8 +43,6 @@ import m5
# import all of the SimObjects
from m5.objects import *
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
# create the system we are going to simulate
system = System()
@@ -56,7 +57,9 @@ system.mem_mode = "timing" # Use timing accesses
system.mem_ranges = [AddrRange("512MB")] # Create an address range
# Create a simple CPU
system.cpu = TimingSimpleCPU()
# You can use ISA-specific CPU models for different workloads:
# `RiscvTimingSimpleCPU`, `ArmTimingSimpleCPU`.
system.cpu = X86TimingSimpleCPU()
# Create a memory bus, a system crossbar, in this case
system.membus = SystemXBar()
@@ -68,12 +71,12 @@ system.cpu.dcache_port = system.membus.cpu_side_ports
# create the interrupt controller for the CPU and connect to the membus
system.cpu.createInterruptController()
# For x86 only, make sure the interrupts are connected to the memory
# Note: these are directly connected to the memory bus and are not cached
if get_runtime_isa() == ISA.X86:
system.cpu.interrupts[0].pio = system.membus.mem_side_ports
system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
# For X86 only we make sure the interrupts care connect to memory.
# Note: these are directly connected to the memory bus and are not cached.
# For other ISA you should remove the following three lines.
system.cpu.interrupts[0].pio = system.membus.mem_side_ports
system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = MemCtrl()
@@ -84,18 +87,14 @@ system.mem_ctrl.port = system.membus.mem_side_ports
# Connect the system up to the membus
system.system_port = system.membus.cpu_side_ports
# get ISA for the binary to run.
isa = get_runtime_isa()
# Default to running 'hello', use the compiled ISA to find the binary
# grab the specific path to the binary
# Here we set the X86 "hello world" binary. With other ISAs you must specify
# workloads compiled to those ISAs. Other "hello world" binaries for other ISAs
# can be found in "tests/test-progs/hello".
thispath = os.path.dirname(os.path.realpath(__file__))
binary = os.path.join(
thispath,
"../../../",
"tests/test-progs/hello/bin/",
isa.name.lower(),
"linux/hello",
"tests/test-progs/hello/bin/x86/linux/hello",
)
system.workload = SEWorkload.init_compatible(binary)

20
configs/learning_gem5/part1/two_level.py
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@@ -43,7 +43,6 @@ import m5
# import all of the SimObjects
from m5.objects import *
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
# Add the common scripts to our path
@@ -55,18 +54,13 @@ from caches import *
# import the SimpleOpts module
from common import SimpleOpts
# get ISA for the default binary to run. This is mostly for simple testing
isa = get_runtime_isa()
# Default to running 'hello', use the compiled ISA to find the binary
# grab the specific path to the binary
thispath = os.path.dirname(os.path.realpath(__file__))
default_binary = os.path.join(
thispath,
"../../../",
"tests/test-progs/hello/bin/",
isa.name.lower(),
"linux/hello",
"tests/test-progs/hello/bin/x86/linux/hello",
)
# Binary to execute
@@ -88,7 +82,7 @@ system.mem_mode = "timing" # Use timing accesses
system.mem_ranges = [AddrRange("512MB")] # Create an address range
# Create a simple CPU
system.cpu = TimingSimpleCPU()
system.cpu = X86TimingSimpleCPU()
# Create an L1 instruction and data cache
system.cpu.icache = L1ICache(args)
@@ -117,13 +111,9 @@ system.l2cache.connectMemSideBus(system.membus)
# create the interrupt controller for the CPU
system.cpu.createInterruptController()
# For x86 only, make sure the interrupts are connected to the memory
# Note: these are directly connected to the memory bus and are not cached
if isa == ISA.X86:
system.cpu.interrupts[0].pio = system.membus.mem_side_ports
system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
system.cpu.interrupts[0].pio = system.membus.mem_side_ports
system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
# Connect the system up to the membus
system.system_port = system.membus.cpu_side_ports

2
configs/learning_gem5/part2/simple_cache.py
View File

@@ -50,7 +50,7 @@ system.mem_mode = "timing" # Use timing accesses
system.mem_ranges = [AddrRange("512MB")] # Create an address range
# Create a simple CPU
system.cpu = TimingSimpleCPU()
system.cpu = X86TimingSimpleCPU()
# Create a memory bus, a coherent crossbar, in this case
system.membus = SystemXBar()

2
configs/learning_gem5/part2/simple_memobj.py
View File

@@ -50,7 +50,7 @@ system.mem_mode = "timing" # Use timing accesses
system.mem_ranges = [AddrRange("512MB")] # Create an address range
# Create a simple CPU
system.cpu = TimingSimpleCPU()
system.cpu = X86TimingSimpleCPU()
# Create the simple memory object
system.memobj = SimpleMemobj()

8
configs/learning_gem5/part3/msi_caches.py
View File

@@ -39,8 +39,6 @@ import math
from m5.defines import buildEnv
from m5.util import fatal, panic
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
from m5.objects import *
@@ -148,10 +146,10 @@ class L1Cache(L1Cache_Controller):
1. The O3 model must keep the LSQ coherent with the caches
2. The x86 mwait instruction is built on top of coherence
3. The local exclusive monitor in ARM systems
As this is an X86 simulation we return True.
"""
if type(cpu) is DerivO3CPU or get_runtime_isa() in (ISA.X86, ISA.ARM):
return True
return False
return True
def connectQueues(self, ruby_system):
"""Connect all of the queues for this controller."""

8
configs/learning_gem5/part3/ruby_caches_MI_example.py
View File

@@ -41,8 +41,6 @@ import math
from m5.defines import buildEnv
from m5.util import fatal, panic
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
from m5.objects import *
@@ -146,10 +144,10 @@ class L1Cache(L1Cache_Controller):
1. The O3 model must keep the LSQ coherent with the caches
2. The x86 mwait instruction is built on top of coherence
3. The local exclusive monitor in ARM systems
As this is an X86 simulation we return True.
"""
if type(cpu) is DerivO3CPU or get_runtime_isa() in (ISA.X86, ISA.ARM):
return True
return False
return True
def connectQueues(self, ruby_system):
"""Connect all of the queues for this controller."""

10
configs/learning_gem5/part3/simple_ruby.py
View File

@@ -42,7 +42,6 @@ import m5
# import all of the SimObjects
from m5.objects import *
from gem5.runtime import get_runtime_isa
# Needed for running C++ threads
m5.util.addToPath("../../")
@@ -65,7 +64,7 @@ system.mem_mode = "timing" # Use timing accesses
system.mem_ranges = [AddrRange("512MB")] # Create an address range
# Create a pair of simple CPUs
system.cpu = [TimingSimpleCPU() for i in range(2)]
system.cpu = [X86TimingSimpleCPU() for i in range(2)]
# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = MemCtrl()
@@ -80,18 +79,13 @@ for cpu in system.cpu:
system.caches = MyCacheSystem()
system.caches.setup(system, system.cpu, [system.mem_ctrl])
# get ISA for the binary to run.
isa = get_runtime_isa()
# Run application and use the compiled ISA to find the binary
# grab the specific path to the binary
thispath = os.path.dirname(os.path.realpath(__file__))
binary = os.path.join(
thispath,
"../../../",
"tests/test-progs/threads/bin/",
isa.name.lower(),
"linux/threads",
"tests/test-progs/threads/bin/x86/linux/threads",
)
# Create a process for a simple "multi-threaded" application