stdlib: Added RiscvMatched prebuilt board
Modeled after the HiFive Unmatched. For the cache, we inherited from AbstractClassicCacheHierarchy and AbstractTwoLevelCacheHierarchy to make a PrivateL1PrivateL2 hierarchy with the same associativity and sizes as the board. However, the L2 Size is kept as a parameter that can be set by the user. The core is in-order, therefore we inherited from RISC-V MinorCPU and used the same pipeline parameters as the ARM HPI CPU, except the decodeToExecuteForwardDelay, which was increased to 2 to avoid a PMC access fault. For the processor, we initialized the core with an ID so that we can return 4 cores in FS mode, which is the same as the real system, and 1 in SE mode. For the memory, we just have a single channel DDR4_2400 with a size of 16 GB and starting at 0x80000000. For the board, we declared a Boolean variable as a parameter to assign whether it is in FS mode or not. We inherited from KernelDiskWorkload and SEBinaryWorkload and initialized the components of the board according to the Boolean. The other parameters are the clock frequency and the L2 cache size. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1257 Change-Id: Ic2c066bb3a41dc2f42566ce971f9a665542f9771 Co-authored-by: Jasjeet Rangi <jasrangi@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63411 Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu> Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
kunpai
@@ -224,6 +224,14 @@ PySource('gem5.components.processors',
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PySource('gem5.prebuilt', 'gem5/prebuilt/__init__.py')
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PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/__init__.py')
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PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/x86_demo_board.py')
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PySource('gem5.prebuilt.riscvmatched',
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'gem5/prebuilt/riscvmatched/riscvmatched_board.py')
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PySource('gem5.prebuilt.riscvmatched',
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'gem5/prebuilt/riscvmatched/riscvmatched_cache.py')
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PySource('gem5.prebuilt.riscvmatched',
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'gem5/prebuilt/riscvmatched/riscvmatched_processor.py')
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PySource('gem5.prebuilt.riscvmatched',
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'gem5/prebuilt/riscvmatched/riscvmatched_core.py')
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PySource('gem5.resources', 'gem5/resources/__init__.py')
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PySource('gem5.resources', 'gem5/resources/downloader.py')
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PySource('gem5.resources', 'gem5/resources/md5_utils.py')
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594
src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
Normal file
594
src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
Normal file
@@ -0,0 +1,594 @@
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# Copyright (c) 2022 The Regents of the University of California
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# Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import os
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import re
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from typing import List, Optional
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from gem5.utils.override import overrides
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from gem5.components.boards.abstract_system_board import AbstractSystemBoard
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from gem5.components.boards.kernel_disk_workload import KernelDiskWorkload
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from gem5.components.boards.se_binary_workload import SEBinaryWorkload
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from gem5.resources.resource import AbstractResource
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from gem5.components.memory import SingleChannelDDR4_2400
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from gem5.utils.requires import requires
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from gem5.isas import ISA
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from .riscvmatched_cache import RISCVMatchedCacheHierarchy
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from .riscvmatched_processor import U74Processor
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from gem5.isas import ISA
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import m5
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from m5.objects import (
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BadAddr,
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Bridge,
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PMAChecker,
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RiscvLinux,
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AddrRange,
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IOXBar,
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RiscvRTC,
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HiFive,
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IGbE_e1000,
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CowDiskImage,
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RawDiskImage,
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RiscvMmioVirtIO,
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VirtIOBlock,
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VirtIORng,
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Frequency,
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Port,
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)
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from m5.util.fdthelper import (
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Fdt,
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FdtNode,
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FdtProperty,
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FdtPropertyStrings,
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FdtPropertyWords,
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FdtState,
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)
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def U74Memory():
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"""
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Memory for the U74 board.
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DDR4 Subsystem with 16GB of memory.
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Starts at 0x80000000.
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Details at: Section 23, page 195 of the datasheet.
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return: ChanneledMemory
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"""
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memory = SingleChannelDDR4_2400("16GB")
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memory.set_memory_range(
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[AddrRange(start=0x80000000, size=memory.get_size())]
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)
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return memory
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class RISCVMatchedBoard(
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AbstractSystemBoard, KernelDiskWorkload, SEBinaryWorkload
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):
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"""
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A board capable of full system simulation for RISC-V
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At a high-level, this is based on the HiFive Unmatched board from SiFive.
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Based on : src/python/gem5/components/boards/riscv_board.py
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This board assumes that you will be booting Linux for fullsystem emulation.
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The frequency of the RTC for the system is set to 1MHz.
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Details can be found on page 77, section 7.1 of the datasheet.
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Datasheet for inbuilt params can be found here: https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
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NOTE: FS Mode does not work yet.
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"""
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def __init__(
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self,
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clk_freq: str = "1.2GHz",
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l2_size: str = "2MB",
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is_fs: bool = False,
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) -> None:
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"""
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:param clk_freq: The clock frequency of the system,
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default: 1.2GHz
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:param l2_size: The size of the L2 cache,
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default: 2MB
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:param is_fs: Whether the system is a full system or not,
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default: False (SE Mode)
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"""
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requires(isa_required=ISA.RISCV)
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self._fs = is_fs
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cache_hierarchy = RISCVMatchedCacheHierarchy(l2_size=l2_size)
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memory = U74Memory()
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processor = U74Processor(is_fs=is_fs)
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super().__init__(
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clk_freq=clk_freq, # real system is 1.0 to 1.5 GHz
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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)
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@overrides(AbstractSystemBoard)
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def _setup_board(self) -> None:
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if self._fs:
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self.workload = RiscvLinux()
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# Contains a CLINT, PLIC, UART, and some functions for the dtb, etc.
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self.platform = HiFive()
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# Note: This only works with single threaded cores.
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self.platform.plic.n_contexts = self.processor.get_num_cores() * 2
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self.platform.attachPlic()
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self.platform.clint.num_threads = self.processor.get_num_cores()
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# Add the RTC
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self.platform.rtc = RiscvRTC(
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frequency=Frequency("1MHz")
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) # page 77, section 7.1
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self.platform.clint.int_pin = self.platform.rtc.int_pin
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# Incoherent I/O bus
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self.iobus = IOXBar()
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self.iobus.badaddr_responder = BadAddr()
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self.iobus.default = self.iobus.badaddr_responder.pio
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# The virtio disk
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self.disk = RiscvMmioVirtIO(
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vio=VirtIOBlock(),
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interrupt_id=0x8,
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pio_size=4096,
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pio_addr=0x10008000,
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)
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# The virtio rng
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self.rng = RiscvMmioVirtIO(
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vio=VirtIORng(),
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interrupt_id=0x8,
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pio_size=4096,
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pio_addr=0x10007000,
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)
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# Note: This overrides the platform's code because the platform isn't
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# general enough.
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self._on_chip_devices = [self.platform.clint, self.platform.plic]
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self._off_chip_devices = [self.platform.uart, self.disk, self.rng]
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else:
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pass
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def _setup_io_devices(self) -> None:
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"""Connect the I/O devices to the I/O bus in FS mode."""
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if self._fs:
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# Add PCI
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self.platform.pci_host.pio = self.iobus.mem_side_ports
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# Add Ethernet card
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self.ethernet = IGbE_e1000(
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pci_bus=0,
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pci_dev=0,
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pci_func=0,
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InterruptLine=1,
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InterruptPin=1,
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)
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self.ethernet.host = self.platform.pci_host
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self.ethernet.pio = self.iobus.mem_side_ports
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self.ethernet.dma = self.iobus.cpu_side_ports
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if self.get_cache_hierarchy().is_ruby():
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for device in self._off_chip_devices + self._on_chip_devices:
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device.pio = self.iobus.mem_side_ports
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else:
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for device in self._off_chip_devices:
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device.pio = self.iobus.mem_side_ports
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for device in self._on_chip_devices:
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device.pio = self.get_cache_hierarchy().get_mem_side_port()
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self.bridge = Bridge(delay="10ns")
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self.bridge.mem_side_port = self.iobus.cpu_side_ports
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self.bridge.cpu_side_port = (
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self.get_cache_hierarchy().get_mem_side_port()
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)
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self.bridge.ranges = [
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AddrRange(dev.pio_addr, size=dev.pio_size)
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for dev in self._off_chip_devices
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]
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# PCI
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self.bridge.ranges.append(AddrRange(0x2F000000, size="16MB"))
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self.bridge.ranges.append(AddrRange(0x30000000, size="256MB"))
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self.bridge.ranges.append(AddrRange(0x40000000, size="512MB"))
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def _setup_pma(self) -> None:
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"""Set the PMA devices on each core"""
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uncacheable_range = [
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AddrRange(dev.pio_addr, size=dev.pio_size)
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for dev in self._on_chip_devices + self._off_chip_devices
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]
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# PCI
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uncacheable_range.append(AddrRange(0x2F000000, size="16MB"))
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uncacheable_range.append(AddrRange(0x30000000, size="256MB"))
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uncacheable_range.append(AddrRange(0x40000000, size="512MB"))
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# TODO: Not sure if this should be done per-core like in the example
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for cpu in self.get_processor().get_cores():
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cpu.get_mmu().pma_checker = PMAChecker(
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uncacheable=uncacheable_range
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)
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@overrides(AbstractSystemBoard)
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def has_dma_ports(self) -> bool:
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return False
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@overrides(AbstractSystemBoard)
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def get_dma_ports(self) -> List[Port]:
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raise NotImplementedError(
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"RISCVBoard does not have DMA Ports. "
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"Use `has_dma_ports()` to check this."
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)
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@overrides(AbstractSystemBoard)
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def has_io_bus(self) -> bool:
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return self._fs
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@overrides(AbstractSystemBoard)
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def get_io_bus(self) -> IOXBar:
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if self._fs:
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return self.iobus
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else:
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raise NotImplementedError(
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"HiFiveBoard does not have an IO bus. "
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"Use `has_io_bus()` to check this."
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)
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@overrides(AbstractSystemBoard)
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def has_coherent_io(self) -> bool:
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return self._fs
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@overrides(AbstractSystemBoard)
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def get_mem_side_coherent_io_port(self) -> Port:
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if self._fs:
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return self.iobus.mem_side_ports
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else:
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raise NotImplementedError(
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"HiFiveBoard does not have any I/O ports. Use has_coherent_io to "
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"check this."
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)
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@overrides(AbstractSystemBoard)
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def _setup_memory_ranges(self):
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"""
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Starting range for the DDR memory is 0x80000000.
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Details can be found on page 201, section 23.2.3 of the datasheet.
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"""
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if self._fs:
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memory = self.get_memory()
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mem_size = memory.get_size()
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self.mem_ranges = [AddrRange(start=0x80000000, size=mem_size)]
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memory.set_memory_range(self.mem_ranges)
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else:
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memory = self.get_memory()
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# The SE board just has one memory range that is the size of the
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# memory.
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self.mem_ranges = [AddrRange(memory.get_size())]
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memory.set_memory_range(self.mem_ranges)
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def generate_device_tree(self, outdir: str) -> None:
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"""Creates the dtb and dts files.
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Creates two files in the outdir: 'device.dtb' and 'device.dts'
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:param outdir: Directory to output the files
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"""
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state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
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root = FdtNode("/")
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root.append(state.addrCellsProperty())
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root.append(state.sizeCellsProperty())
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root.appendCompatible(["riscv-virtio"])
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for mem_range in self.mem_ranges:
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node = FdtNode("memory@%x" % int(mem_range.start))
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node.append(FdtPropertyStrings("device_type", ["memory"]))
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node.append(
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FdtPropertyWords(
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"reg",
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state.addrCells(mem_range.start)
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+ state.sizeCells(mem_range.size()),
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)
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)
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root.append(node)
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# See Documentation/devicetree/bindings/riscv/cpus.txt for details.
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cpus_node = FdtNode("cpus")
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cpus_state = FdtState(addr_cells=1, size_cells=0)
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cpus_node.append(cpus_state.addrCellsProperty())
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cpus_node.append(cpus_state.sizeCellsProperty())
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# Used by the CLINT driver to set the timer frequency. Value taken from
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# RISC-V kernel docs (Note: freedom-u540 is actually 1MHz)
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cpus_node.append(FdtPropertyWords("timebase-frequency", [100000000]))
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for i, core in enumerate(self.get_processor().get_cores()):
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node = FdtNode(f"cpu@{i}")
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node.append(FdtPropertyStrings("device_type", "cpu"))
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node.append(FdtPropertyWords("reg", state.CPUAddrCells(i)))
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node.append(FdtPropertyStrings("mmu-type", "riscv,sv48"))
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node.append(FdtPropertyStrings("status", "okay"))
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node.append(FdtPropertyStrings("riscv,isa", "rv64imafdc"))
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freq = self.clk_domain.clock[0].frequency
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node.append(FdtPropertyWords("clock-frequency", freq))
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node.appendCompatible(["riscv"])
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int_phandle = state.phandle(f"cpu@{i}.int_state")
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node.appendPhandle(f"cpu@{i}")
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int_node = FdtNode("interrupt-controller")
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int_state = FdtState(interrupt_cells=1)
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int_phandle = int_state.phandle(f"cpu@{i}.int_state")
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int_node.append(int_state.interruptCellsProperty())
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int_node.append(FdtProperty("interrupt-controller"))
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int_node.appendCompatible("riscv,cpu-intc")
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int_node.append(FdtPropertyWords("phandle", [int_phandle]))
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|
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node.append(int_node)
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cpus_node.append(node)
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root.append(cpus_node)
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|
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soc_node = FdtNode("soc")
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soc_state = FdtState(addr_cells=2, size_cells=2)
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soc_node.append(soc_state.addrCellsProperty())
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soc_node.append(soc_state.sizeCellsProperty())
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soc_node.append(FdtProperty("ranges"))
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soc_node.appendCompatible(["simple-bus"])
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# CLINT node
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clint = self.platform.clint
|
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clint_node = clint.generateBasicPioDeviceNode(
|
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soc_state, "clint", clint.pio_addr, clint.pio_size
|
||||
)
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||||
int_extended = list()
|
||||
for i, core in enumerate(self.get_processor().get_cores()):
|
||||
phandle = soc_state.phandle(f"cpu@{i}.int_state")
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||||
int_extended.append(phandle)
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||||
int_extended.append(0x3)
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||||
int_extended.append(phandle)
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||||
int_extended.append(0x7)
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||||
clint_node.append(
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||||
FdtPropertyWords("interrupts-extended", int_extended)
|
||||
)
|
||||
clint_node.appendCompatible(["riscv,clint0"])
|
||||
soc_node.append(clint_node)
|
||||
|
||||
# PLIC node
|
||||
plic = self.platform.plic
|
||||
plic_node = plic.generateBasicPioDeviceNode(
|
||||
soc_state, "plic", plic.pio_addr, plic.pio_size
|
||||
)
|
||||
|
||||
int_state = FdtState(addr_cells=0, interrupt_cells=1)
|
||||
plic_node.append(int_state.addrCellsProperty())
|
||||
plic_node.append(int_state.interruptCellsProperty())
|
||||
|
||||
phandle = int_state.phandle(plic)
|
||||
plic_node.append(FdtPropertyWords("phandle", [phandle]))
|
||||
plic_node.append(FdtPropertyWords("riscv,ndev", [plic.n_src - 1]))
|
||||
|
||||
int_extended = list()
|
||||
for i, core in enumerate(self.get_processor().get_cores()):
|
||||
phandle = state.phandle(f"cpu@{i}.int_state")
|
||||
int_extended.append(phandle)
|
||||
int_extended.append(0xB)
|
||||
int_extended.append(phandle)
|
||||
int_extended.append(0x9)
|
||||
|
||||
plic_node.append(FdtPropertyWords("interrupts-extended", int_extended))
|
||||
plic_node.append(FdtProperty("interrupt-controller"))
|
||||
plic_node.appendCompatible(["riscv,plic0"])
|
||||
|
||||
soc_node.append(plic_node)
|
||||
|
||||
# PCI
|
||||
pci_state = FdtState(
|
||||
addr_cells=3, size_cells=2, cpu_cells=1, interrupt_cells=1
|
||||
)
|
||||
pci_node = FdtNode("pci")
|
||||
|
||||
if int(self.platform.pci_host.conf_device_bits) == 8:
|
||||
pci_node.appendCompatible("pci-host-cam-generic")
|
||||
elif int(self.platform.pci_host.conf_device_bits) == 12:
|
||||
pci_node.appendCompatible("pci-host-ecam-generic")
|
||||
else:
|
||||
m5.fatal("No compatibility string for the set conf_device_width")
|
||||
|
||||
pci_node.append(FdtPropertyStrings("device_type", ["pci"]))
|
||||
|
||||
# Cell sizes of child nodes/peripherals
|
||||
pci_node.append(pci_state.addrCellsProperty())
|
||||
pci_node.append(pci_state.sizeCellsProperty())
|
||||
pci_node.append(pci_state.interruptCellsProperty())
|
||||
# PCI address for CPU
|
||||
pci_node.append(
|
||||
FdtPropertyWords(
|
||||
"reg",
|
||||
soc_state.addrCells(self.platform.pci_host.conf_base)
|
||||
+ soc_state.sizeCells(self.platform.pci_host.conf_size),
|
||||
)
|
||||
)
|
||||
|
||||
# Ranges mapping
|
||||
# For now some of this is hard coded, because the PCI module does not
|
||||
# have a proper full understanding of the memory map, but adapting the
|
||||
# PCI module is beyond the scope of what I'm trying to do here.
|
||||
# Values are taken from the ARM VExpress_GEM5_V1 platform.
|
||||
ranges = []
|
||||
# Pio address range
|
||||
ranges += self.platform.pci_host.pciFdtAddr(space=1, addr=0)
|
||||
ranges += soc_state.addrCells(self.platform.pci_host.pci_pio_base)
|
||||
ranges += pci_state.sizeCells(0x10000) # Fixed size
|
||||
|
||||
# AXI memory address range
|
||||
ranges += self.platform.pci_host.pciFdtAddr(space=2, addr=0)
|
||||
ranges += soc_state.addrCells(self.platform.pci_host.pci_mem_base)
|
||||
ranges += pci_state.sizeCells(0x40000000) # Fixed size
|
||||
pci_node.append(FdtPropertyWords("ranges", ranges))
|
||||
|
||||
# Interrupt mapping
|
||||
plic_handle = int_state.phandle(plic)
|
||||
int_base = self.platform.pci_host.int_base
|
||||
|
||||
interrupts = []
|
||||
|
||||
for i in range(int(self.platform.pci_host.int_count)):
|
||||
interrupts += self.platform.pci_host.pciFdtAddr(
|
||||
device=i, addr=0
|
||||
) + [int(i) + 1, plic_handle, int(int_base) + i]
|
||||
|
||||
pci_node.append(FdtPropertyWords("interrupt-map", interrupts))
|
||||
|
||||
int_count = int(self.platform.pci_host.int_count)
|
||||
if int_count & (int_count - 1):
|
||||
fatal("PCI interrupt count should be power of 2")
|
||||
|
||||
intmask = self.platform.pci_host.pciFdtAddr(
|
||||
device=int_count - 1, addr=0
|
||||
) + [0x0]
|
||||
pci_node.append(FdtPropertyWords("interrupt-map-mask", intmask))
|
||||
|
||||
if self.platform.pci_host._dma_coherent:
|
||||
pci_node.append(FdtProperty("dma-coherent"))
|
||||
|
||||
soc_node.append(pci_node)
|
||||
|
||||
# UART node
|
||||
uart = self.platform.uart
|
||||
uart_node = uart.generateBasicPioDeviceNode(
|
||||
soc_state, "uart", uart.pio_addr, uart.pio_size
|
||||
)
|
||||
uart_node.append(
|
||||
FdtPropertyWords("interrupts", [self.platform.uart_int_id])
|
||||
)
|
||||
uart_node.append(FdtPropertyWords("clock-frequency", [0x384000]))
|
||||
uart_node.append(
|
||||
FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
|
||||
)
|
||||
uart_node.appendCompatible(["ns8250"])
|
||||
soc_node.append(uart_node)
|
||||
|
||||
# VirtIO MMIO disk node
|
||||
disk = self.disk
|
||||
disk_node = disk.generateBasicPioDeviceNode(
|
||||
soc_state, "virtio_mmio", disk.pio_addr, disk.pio_size
|
||||
)
|
||||
disk_node.append(FdtPropertyWords("interrupts", [disk.interrupt_id]))
|
||||
disk_node.append(
|
||||
FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
|
||||
)
|
||||
disk_node.appendCompatible(["virtio,mmio"])
|
||||
soc_node.append(disk_node)
|
||||
|
||||
# VirtIO MMIO rng node
|
||||
rng = self.rng
|
||||
rng_node = rng.generateBasicPioDeviceNode(
|
||||
soc_state, "virtio_mmio", rng.pio_addr, rng.pio_size
|
||||
)
|
||||
rng_node.append(FdtPropertyWords("interrupts", [rng.interrupt_id]))
|
||||
rng_node.append(
|
||||
FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
|
||||
)
|
||||
rng_node.appendCompatible(["virtio,mmio"])
|
||||
soc_node.append(rng_node)
|
||||
|
||||
root.append(soc_node)
|
||||
|
||||
fdt = Fdt()
|
||||
fdt.add_rootnode(root)
|
||||
fdt.writeDtsFile(os.path.join(outdir, "device.dts"))
|
||||
fdt.writeDtbFile(os.path.join(outdir, "device.dtb"))
|
||||
|
||||
@overrides(KernelDiskWorkload)
|
||||
def get_disk_device(self):
|
||||
return "/dev/vda"
|
||||
|
||||
@overrides(KernelDiskWorkload)
|
||||
def _add_disk_to_board(self, disk_image: AbstractResource):
|
||||
image = CowDiskImage(
|
||||
child=RawDiskImage(read_only=True), read_only=False
|
||||
)
|
||||
image.child.image_file = disk_image.get_local_path()
|
||||
self.disk.vio.image = image
|
||||
|
||||
# Note: The below is a bit of a hack. We need to wait to generate the
|
||||
# device tree until after the disk is set up. Now that the disk and
|
||||
# workload are set, we can generate the device tree file.
|
||||
self._setup_io_devices()
|
||||
self._setup_pma()
|
||||
|
||||
# Default DTB address if bbl is built with --with-dts option
|
||||
self.workload.dtb_addr = 0x87E00000
|
||||
|
||||
self.generate_device_tree(m5.options.outdir)
|
||||
self.workload.dtb_filename = os.path.join(
|
||||
m5.options.outdir, "device.dtb"
|
||||
)
|
||||
|
||||
@overrides(KernelDiskWorkload)
|
||||
def get_default_kernel_args(self) -> List[str]:
|
||||
return ["console=ttyS0", "root={root_value}", "ro"]
|
||||
|
||||
@overrides(KernelDiskWorkload)
|
||||
def set_kernel_disk_workload(
|
||||
self,
|
||||
kernel: AbstractResource,
|
||||
disk_image: AbstractResource,
|
||||
bootloader: Optional[AbstractResource] = None,
|
||||
readfile: Optional[str] = None,
|
||||
readfile_contents: Optional[str] = None,
|
||||
kernel_args: Optional[List[str]] = None,
|
||||
exit_on_work_items: bool = True,
|
||||
) -> None:
|
||||
self.workload = RiscvLinux()
|
||||
KernelDiskWorkload.set_kernel_disk_workload(
|
||||
self=self,
|
||||
kernel=kernel,
|
||||
disk_image=disk_image,
|
||||
bootloader=bootloader,
|
||||
readfile=readfile,
|
||||
readfile_contents=readfile_contents,
|
||||
kernel_args=kernel_args,
|
||||
exit_on_work_items=exit_on_work_items,
|
||||
)
|
||||
173
src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py
Normal file
173
src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py
Normal file
@@ -0,0 +1,173 @@
|
||||
# Copyright (c) 2022 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
from gem5.components.cachehierarchies.abstract_cache_hierarchy import (
|
||||
AbstractCacheHierarchy,
|
||||
)
|
||||
from gem5.components.cachehierarchies.classic.abstract_classic_cache_hierarchy import (
|
||||
AbstractClassicCacheHierarchy,
|
||||
)
|
||||
from gem5.components.cachehierarchies.abstract_two_level_cache_hierarchy import (
|
||||
AbstractTwoLevelCacheHierarchy,
|
||||
)
|
||||
from gem5.components.cachehierarchies.classic.caches.l1dcache import L1DCache
|
||||
from gem5.components.cachehierarchies.classic.caches.l1icache import L1ICache
|
||||
from gem5.components.cachehierarchies.classic.caches.l2cache import L2Cache
|
||||
from gem5.components.cachehierarchies.classic.caches.mmu_cache import MMUCache
|
||||
from gem5.components.boards.abstract_board import AbstractBoard
|
||||
from gem5.isas import ISA
|
||||
from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port
|
||||
|
||||
from gem5.utils.override import *
|
||||
|
||||
|
||||
class RISCVMatchedCacheHierarchy(
|
||||
AbstractClassicCacheHierarchy, AbstractTwoLevelCacheHierarchy
|
||||
):
|
||||
"""
|
||||
|
||||
A cache setup where each core has a private L1 Data and Instruction Cache,
|
||||
and a private L2 cache.
|
||||
The HiFive board has a partially inclusive cache hierarchy, hence this hierarchy is chosen.
|
||||
The details of the cache hierarchy are in Table 7, page 36 of the datasheet.
|
||||
|
||||
- L1 Instruction Cache:
|
||||
- 32 KiB 4-way set associative
|
||||
- L1 Data Cache
|
||||
- 32 KiB 8-way set associative
|
||||
- L2 Cache
|
||||
- 2 MiB 16-way set associative
|
||||
|
||||
"""
|
||||
|
||||
def __init__(
|
||||
self,
|
||||
l2_size: str,
|
||||
) -> None:
|
||||
"""
|
||||
:param l2_size: The size of the L2 Cache (e.g., "256kB").
|
||||
:type l2_size: str
|
||||
"""
|
||||
AbstractClassicCacheHierarchy.__init__(self=self)
|
||||
AbstractTwoLevelCacheHierarchy.__init__(
|
||||
self,
|
||||
l1i_size="32kB",
|
||||
l1i_assoc=4,
|
||||
l1d_size="32kB",
|
||||
l1d_assoc=8,
|
||||
l2_size=l2_size,
|
||||
l2_assoc=16,
|
||||
)
|
||||
|
||||
self.membus = SystemXBar(width=64)
|
||||
self.membus.badaddr_responder = BadAddr()
|
||||
self.membus.default = self.membus.badaddr_responder.pio
|
||||
|
||||
@overrides(AbstractClassicCacheHierarchy)
|
||||
def get_mem_side_port(self) -> Port:
|
||||
return self.membus.mem_side_ports
|
||||
|
||||
@overrides(AbstractClassicCacheHierarchy)
|
||||
def get_cpu_side_port(self) -> Port:
|
||||
return self.membus.cpu_side_ports
|
||||
|
||||
@overrides(AbstractCacheHierarchy)
|
||||
def incorporate_cache(self, board: AbstractBoard) -> None:
|
||||
|
||||
# Set up the system port for functional access from the simulator.
|
||||
board.connect_system_port(self.membus.cpu_side_ports)
|
||||
|
||||
for cntr in board.get_memory().get_memory_controllers():
|
||||
cntr.port = self.membus.mem_side_ports
|
||||
|
||||
self.l1icaches = [
|
||||
L1ICache(size=self._l1i_size, assoc=self._l1i_assoc)
|
||||
for i in range(board.get_processor().get_num_cores())
|
||||
]
|
||||
self.l1dcaches = [
|
||||
L1DCache(size=self._l1d_size, assoc=self._l1d_assoc)
|
||||
for i in range(board.get_processor().get_num_cores())
|
||||
]
|
||||
self.l2buses = [
|
||||
L2XBar() for i in range(board.get_processor().get_num_cores())
|
||||
]
|
||||
self.l2caches = [
|
||||
L2Cache(size=self._l2_size, assoc=self._l2_assoc)
|
||||
for i in range(board.get_processor().get_num_cores())
|
||||
]
|
||||
# ITLB Page walk caches
|
||||
self.iptw_caches = [
|
||||
MMUCache(size="4KiB")
|
||||
for _ in range(board.get_processor().get_num_cores())
|
||||
]
|
||||
# DTLB Page walk caches
|
||||
self.dptw_caches = [
|
||||
MMUCache(size="4KiB")
|
||||
for _ in range(board.get_processor().get_num_cores())
|
||||
]
|
||||
|
||||
if board.has_coherent_io():
|
||||
self._setup_io_cache(board)
|
||||
|
||||
for i, cpu in enumerate(board.get_processor().get_cores()):
|
||||
|
||||
cpu.connect_icache(self.l1icaches[i].cpu_side)
|
||||
cpu.connect_dcache(self.l1dcaches[i].cpu_side)
|
||||
|
||||
self.l1icaches[i].mem_side = self.l2buses[i].cpu_side_ports
|
||||
self.l1dcaches[i].mem_side = self.l2buses[i].cpu_side_ports
|
||||
self.iptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports
|
||||
self.dptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports
|
||||
|
||||
self.l2buses[i].mem_side_ports = self.l2caches[i].cpu_side
|
||||
|
||||
self.membus.cpu_side_ports = self.l2caches[i].mem_side
|
||||
|
||||
cpu.connect_walker_ports(
|
||||
self.iptw_caches[i].cpu_side, self.dptw_caches[i].cpu_side
|
||||
)
|
||||
|
||||
if board.get_processor().get_isa() == ISA.X86:
|
||||
int_req_port = self.membus.mem_side_ports
|
||||
int_resp_port = self.membus.cpu_side_ports
|
||||
cpu.connect_interrupt(int_req_port, int_resp_port)
|
||||
else:
|
||||
cpu.connect_interrupt()
|
||||
|
||||
def _setup_io_cache(self, board: AbstractBoard) -> None:
|
||||
"""Create a cache for coherent I/O connections"""
|
||||
self.iocache = Cache(
|
||||
assoc=8,
|
||||
tag_latency=50,
|
||||
data_latency=50,
|
||||
response_latency=50,
|
||||
mshrs=20,
|
||||
size="1kB",
|
||||
tgts_per_mshr=12,
|
||||
addr_ranges=board.mem_ranges,
|
||||
)
|
||||
self.iocache.mem_side = self.membus.cpu_side_ports
|
||||
self.iocache.cpu_side = board.get_mem_side_coherent_io_port()
|
||||
168
src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
Normal file
168
src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py
Normal file
@@ -0,0 +1,168 @@
|
||||
# Copyright (c) 2022 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
from typing import Optional
|
||||
from gem5.utils.requires import requires
|
||||
from gem5.components.processors.base_cpu_core import BaseCPUCore
|
||||
from gem5.components.processors.cpu_types import CPUTypes
|
||||
from gem5.isas import ISA
|
||||
from gem5.utils.override import overrides
|
||||
from m5.objects.RiscvCPU import RiscvMinorCPU
|
||||
from m5.objects import (
|
||||
BaseMMU,
|
||||
Port,
|
||||
BaseCPU,
|
||||
Process,
|
||||
)
|
||||
from m5.objects.BaseMinorCPU import *
|
||||
from gem5.isas import ISA
|
||||
|
||||
|
||||
class U74IntFU(MinorDefaultIntFU):
|
||||
opLat = 1
|
||||
|
||||
|
||||
class U74IntMulFU(MinorDefaultIntMulFU):
|
||||
opLat = 3
|
||||
|
||||
|
||||
class U74IntDivFU(MinorDefaultIntDivFU):
|
||||
opLat = 6
|
||||
|
||||
|
||||
class U74FloatSimdFU(MinorDefaultFloatSimdFU):
|
||||
pass
|
||||
|
||||
|
||||
class U74PredFU(MinorDefaultPredFU):
|
||||
pass
|
||||
|
||||
|
||||
class U74MemFU(MinorDefaultMemFU):
|
||||
opLat = 3
|
||||
|
||||
|
||||
class U74MiscFU(MinorDefaultMiscFU):
|
||||
pass
|
||||
|
||||
|
||||
class U74FUPool(MinorFUPool):
|
||||
funcUnits = [
|
||||
U74IntFU(),
|
||||
U74IntFU(),
|
||||
U74IntMulFU(),
|
||||
U74IntDivFU(),
|
||||
U74FloatSimdFU(),
|
||||
U74PredFU(),
|
||||
U74MemFU(),
|
||||
U74MiscFU(),
|
||||
]
|
||||
|
||||
|
||||
class U74BP(TournamentBP):
|
||||
BTBEntries = 16
|
||||
RASSize = 6
|
||||
localHistoryTableSize = 4096 # is 3.6 KiB but gem5 requires power of 2
|
||||
|
||||
indirectBranchPred = SimpleIndirectPredictor()
|
||||
indirectBranchPred.indirectSets = 8
|
||||
|
||||
|
||||
class U74CPU(RiscvMinorCPU):
|
||||
"""
|
||||
The fetch, decode, and execute stage parameters from the ARM HPI CPU
|
||||
This information about the CPU can be found on page 15 of
|
||||
gem5_rsk_gem5-21.2.pdf at https://github.com/arm-university/arm-gem5-rsk
|
||||
|
||||
The only parameter that is changed is the decodeToExecuteForwardDelay.
|
||||
This is changed from 1 to 2 to avoid a PMC address fault.
|
||||
|
||||
"""
|
||||
|
||||
# Fetch1 stage
|
||||
fetch1LineSnapWidth = 0
|
||||
fetch1LineWidth = 0
|
||||
fetch1FetchLimit = 1
|
||||
fetch1ToFetch2ForwardDelay = 1
|
||||
fetch1ToFetch2BackwardDelay = 1
|
||||
|
||||
# Fetch2 stage
|
||||
fetch2InputBufferSize = 2
|
||||
fetch2ToDecodeForwardDelay = 1
|
||||
fetch2CycleInput = True
|
||||
|
||||
# Decode stage
|
||||
decodeInputBufferSize = 3
|
||||
decodeToExecuteForwardDelay = 2
|
||||
decodeInputWidth = 2
|
||||
decodeCycleInput = True
|
||||
|
||||
# Execute stage
|
||||
executeInputWidth = 2
|
||||
executeCycleInput = True
|
||||
executeIssueLimit = 2
|
||||
executeMemoryIssueLimit = 1
|
||||
executeCommitLimit = 2
|
||||
executeMemoryCommitLimit = 1
|
||||
executeInputBufferSize = 7
|
||||
executeMaxAccessesInMemory = 2
|
||||
executeLSQMaxStoreBufferStoresPerCycle = 2
|
||||
executeLSQRequestsQueueSize = 1
|
||||
executeLSQTransfersQueueSize = 2
|
||||
executeLSQStoreBufferSize = 5
|
||||
executeBranchDelay = 1
|
||||
executeSetTraceTimeOnCommit = True
|
||||
executeSetTraceTimeOnIssue = False
|
||||
executeAllowEarlyMemoryIssue = True
|
||||
enableIdling = True
|
||||
|
||||
# Functional Units and Branch Prediction
|
||||
executeFuncUnits = U74FUPool()
|
||||
branchPred = U74BP()
|
||||
|
||||
|
||||
class U74Core(BaseCPUCore):
|
||||
"""
|
||||
U74Core models the core of the HiFive Unmatched board.
|
||||
The core has a single thread.
|
||||
The latencies of the functional units are set to values found in Table 8 on page 40.
|
||||
- IntFU: 1 cycle
|
||||
- IntMulFU: 3 cycles
|
||||
- IntDivFU: 6 cycles (NOTE: latency is variable, but is set to 6 cycles)
|
||||
- MemFU: 3 cycles
|
||||
The branch predictor is a TournamentBP, based on Section 4.2.5 on page 38.
|
||||
- BTBEntries: 16 entries
|
||||
- RASSize: 6 entries
|
||||
- IndirectSets: 8 sets
|
||||
- localHistoryTableSize: 4096 B
|
||||
NOTE: The BHT of the HiFive Board is 3.6KiB but gem5 requires a power of 2, so the BHT is 4096B.
|
||||
"""
|
||||
|
||||
def __init__(
|
||||
self,
|
||||
core_id,
|
||||
):
|
||||
super().__init__(core=U74CPU(cpu_id=core_id), isa=ISA.RISCV)
|
||||
@@ -0,0 +1,55 @@
|
||||
# Copyright (c) 2022 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
from gem5.utils.override import overrides
|
||||
from gem5.components.boards.mem_mode import MemMode
|
||||
|
||||
from m5.util import warn
|
||||
|
||||
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
|
||||
from gem5.components.processors.cpu_types import CPUTypes
|
||||
from gem5.components.boards.abstract_board import AbstractBoard
|
||||
from .riscvmatched_core import U74Core
|
||||
|
||||
|
||||
class U74Processor(BaseCPUProcessor):
|
||||
"""
|
||||
A U74Processor contains a number of cores of U74Core.
|
||||
"""
|
||||
|
||||
def __init__(
|
||||
self,
|
||||
is_fs: bool,
|
||||
) -> None:
|
||||
self._cpu_type = CPUTypes.MINOR
|
||||
super().__init__(cores=self._create_cores(is_fs))
|
||||
|
||||
def _create_cores(self, is_fs: bool):
|
||||
if is_fs:
|
||||
num_cores = 4
|
||||
else:
|
||||
num_cores = 1
|
||||
return [U74Core(core_id=i) for i in range(num_cores)]
|
||||
Reference in New Issue
Block a user