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arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs

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gem5-ARM is not using floatRegs anymore and moved towards the
vecRegs register file (which is used for SIMD&FP + SVE instructions)

Change-Id: I41cfbe10565e4e0db838f98626310a5b14edadb9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23103
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-11-18 13:19:49 +00:00
parent 55a10a13f9
commit 3a5ff476ff
3 changed files with 5 additions and 6 deletions
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8
src/arch/arm/insts/macromem.cc
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@@ -1123,7 +1123,7 @@ VldMultOp64::VldMultOp64(const char *mnem, ExtMachInst machInst,
uint8_t numStructElems, uint8_t numRegs, bool wb) :
PredMacroOp(mnem, machInst, __opClass)
{
RegIndex vx = NumFloatV8ArchRegs / 4;
RegIndex vx = NumVecV8ArchRegs;
RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
bool baseIsSP = isSP((IntRegIndex) rnsp);
@@ -1208,7 +1208,7 @@ VstMultOp64::VstMultOp64(const char *mnem, ExtMachInst machInst,
uint8_t numStructElems, uint8_t numRegs, bool wb) :
PredMacroOp(mnem, machInst, __opClass)
{
RegIndex vx = NumFloatV8ArchRegs / 4;
RegIndex vx = NumVecV8ArchRegs;
RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
bool baseIsSP = isSP((IntRegIndex) rnsp);
@@ -1297,7 +1297,7 @@ VldSingleOp64::VldSingleOp64(const char *mnem, ExtMachInst machInst,
wb(false), replicate(false)
{
RegIndex vx = NumFloatV8ArchRegs / 4;
RegIndex vx = NumVecV8ArchRegs;
RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
bool baseIsSP = isSP((IntRegIndex) rnsp);
@@ -1370,7 +1370,7 @@ VstSingleOp64::VstSingleOp64(const char *mnem, ExtMachInst machInst,
eSize(0), dataSize(0), numStructElems(0), index(0),
wb(false), replicate(false)
{
RegIndex vx = NumFloatV8ArchRegs / 4;
RegIndex vx = NumVecV8ArchRegs;
RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
bool baseIsSP = isSP((IntRegIndex) rnsp);

2
src/arch/arm/kvm/armv8_cpu.cc
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@@ -51,7 +51,7 @@ static_assert(NUM_XREGS == 31, "Unexpected number of aarch64 int. regs.");
// The KVM interface accesses vector registers of 4 single precision
// floats instead of individual registers.
constexpr static unsigned NUM_QREGS = NumFloatV8ArchRegs / 4;
constexpr static unsigned NUM_QREGS = NumVecV8ArchRegs;
static_assert(NUM_QREGS == 32, "Unexpected number of aarch64 vector regs.");
#define EXTRACT_FIELD(v, name) \

1
src/arch/arm/registers.hh
View File

@@ -82,7 +82,6 @@ using VecPredRegContainer = VecPredReg::Container;
const int NumIntArchRegs = NUM_ARCH_INTREGS;
// The number of single precision floating point registers
const int NumFloatV7ArchRegs = 64;
const int NumFloatV8ArchRegs = 128;
const int NumVecV7ArchRegs = 64;
const int NumVecV8ArchRegs = 32;
const int NumVecSpecialRegs = 8;