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arch-x86: Style fixes and use uop args in the media ops.

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Change-Id: I73b125888895acb74db16fc766af2571a73fb147
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42352
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-03-04 06:44:37 -08:00
parent ef59d8504f
commit 39f76bb2b1
7 changed files with 261 additions and 432 deletions
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1
src/arch/x86/SConscript
View File

@@ -50,7 +50,6 @@ Source('emulenv.cc')
Source('faults.cc')
Source('fs_workload.cc')
Source('insts/badmicroop.cc')
Source('insts/micromediaop.cc')
Source('insts/microop.cc')
Source('insts/microregop.cc')
Source('insts/static_inst.cc')

67
src/arch/x86/insts/micromediaop.cc
View File

@@ -1,67 +0,0 @@
/*
* Copyright (c) 2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "arch/x86/insts/micromediaop.hh"
#include <string>
#include "arch/x86/regs/misc.hh"
namespace X86ISA
{
std::string
MediaOpReg::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, instMnem, mnemonic);
printDestReg(response, 0, destSize);
response << ", ";
printSrcReg(response, 0, srcSize);
response << ", ";
printSrcReg(response, 1, srcSize);
return response.str();
}
std::string
MediaOpImm::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
{
std::stringstream response;
printMnemonic(response, instMnem, mnemonic);
printDestReg(response, 0, destSize);
response << ", ";
printSrcReg(response, 0, srcSize);
ccprintf(response, ", %#x", imm8);
return response.str();
}
}

60
src/arch/x86/insts/micromediaop.hh
View File

@@ -44,23 +44,16 @@ enum MediaFlag
class MediaOpBase : public X86MicroopBase
{
protected:
const RegIndex src1;
const RegIndex dest;
const uint8_t srcSize;
const uint8_t destSize;
const uint8_t ext;
static const RegIndex foldOBit = 0;
// Constructor
MediaOpBase(ExtMachInst _machInst,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint8_t _ext,
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
__opClass),
src1(_src1.index()), dest(_dest.index()),
srcSize(_srcSize), destSize(_destSize), ext(_ext)
MediaOpBase(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem,
uint64_t set_flags, OpClass op_class,
uint8_t src_size, uint8_t dest_size, uint8_t _ext) :
X86MicroopBase(mach_inst, mnem, inst_mnem, set_flags, op_class),
srcSize(src_size), destSize(dest_size), ext(_ext)
{}
bool
@@ -86,48 +79,9 @@ class MediaOpBase : public X86MicroopBase
{
return ext & MediaSignedOp;
}
};
class MediaOpReg : public MediaOpBase
{
protected:
const RegIndex src2;
// Constructor
MediaOpReg(ExtMachInst _machInst,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint8_t _ext,
OpClass __opClass) :
MediaOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _srcSize, _destSize, _ext,
__opClass),
src2(_src2.index())
{}
std::string generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override;
};
class MediaOpImm : public MediaOpBase
{
protected:
uint8_t imm8;
// Constructor
MediaOpImm(ExtMachInst _machInst,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint8_t _ext,
OpClass __opClass) :
MediaOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _srcSize, _destSize, _ext,
__opClass),
imm8(_imm8)
{}
std::string generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override;
public:
static constexpr uint8_t dataSize = 0;
};
}

12
src/arch/x86/isa/microops/fpop.isa
View File

@@ -300,7 +300,7 @@ let {{
class Cvtf_i2d(ConvOp):
operands = (fp_dest_op, int_src1_op)
code = '''
X86IntReg intReg = SSrcReg1;
X86IntReg intReg = SrcReg1;
if (REX_W)
FpDestReg = intReg.SR;
else
@@ -309,7 +309,7 @@ let {{
class Cvtf_i2d_hi(ConvOp):
operands = (fp_dest_op, int_src1_op)
code = 'FpDestReg = bits(SSrcReg1, 63, 32);'
code = 'FpDestReg = bits(SrcReg1, 63, 32);'
class Cvtf_d2i(ConvOp):
operands = (int_dest_op, fp_src1_op)
@@ -324,8 +324,8 @@ let {{
operands = (fp_dest_op, int_src1_op, int_src2_op)
code = '''
uint8_t bits[10];
*(uint64_t *)(bits + 0) = SSrcReg1;
*(uint16_t *)(bits + 8) = (uint16_t)SSrcReg2;
*(uint64_t *)(bits + 0) = SrcReg1;
*(uint16_t *)(bits + 8) = (uint16_t)SrcReg2;
FpDestReg = loadFloat80(bits);
'''
@@ -336,7 +336,7 @@ let {{
code = '''
char bits[10];
storeFloat80(bits, FpSrcReg1);
SDestReg = *(uint64_t *)(bits + 0);
DestReg = *(uint64_t *)(bits + 0);
'''
# Convert an x87 register (double) into extended precision and
@@ -346,7 +346,7 @@ let {{
code = '''
char bits[10];
storeFloat80(bits, FpSrcReg1);
SDestReg = *(uint16_t *)(bits + 8);
DestReg = *(uint16_t *)(bits + 8);
'''
# These need to consider size at some point. They'll always use doubles

310
src/arch/x86/isa/microops/mediaop.isa
View File

@@ -27,86 +27,47 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
def template MediaOpExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(op_decl)s;
%(op_rd)s;
%(code)s;
%(code)s;
//Write the resulting state to the execution context
if(fault == NoFault)
{
%(op_wb)s;
}
return fault;
//Write the resulting state to the execution context
if(fault == NoFault) {
%(op_wb)s;
}
return fault;
}
}};
def template MediaOpRegDeclare {{
def template MediaOpDeclare {{
class %(class_name)s : public %(base_class)s
{
private:
%(reg_idx_arr_decl)s;
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint16_t _ext);
template <typename ...Args>
%(class_name)s(ExtMachInst mach_inst, const char *inst_mnem,
uint64_t set_flags, uint8_t src_size, uint8_t dest_size,
uint16_t _ext, Args... args) :
%(base_class)s(mach_inst, "%(mnemonic)s", inst_mnem, set_flags,
%(op_class)s, args..., src_size, dest_size, _ext)
{
%(set_reg_idx_arr)s;
%(constructor)s;
}
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template MediaOpImmDeclare {{
class %(class_name)s : public %(base_class)s
{
private:
%(reg_idx_arr_decl)s;
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint16_t _ext);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template MediaOpRegConstructor {{
%(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
_src1, _src2, _dest, _srcSize, _destSize, _ext,
%(op_class)s)
{
%(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template MediaOpImmConstructor {{
%(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
_src1, _imm8, _dest, _srcSize, _destSize, _ext,
%(op_class)s)
{
%(set_reg_idx_arr)s;
%(constructor)s;
}
}};
let {{
# Make these empty strings so that concatenating onto
# them will always work.
@@ -114,27 +75,33 @@ let {{
decoder_output = ""
exec_output = ""
immTemplates = (
MediaOpImmDeclare,
MediaOpImmConstructor,
MediaOpExecute)
int_dest_op = "X86ISA::IntDestOp"
fp_dest_op = "X86ISA::FloatDestOp"
regTemplates = (
MediaOpRegDeclare,
MediaOpRegConstructor,
MediaOpExecute)
int_src1_op = "X86ISA::IntSrc1Op"
fp_src1_op = "X86ISA::FloatSrc1Op"
int_src2_op = "X86ISA::IntSrc2Op"
fp_src2_op = "X86ISA::FloatSrc2Op"
imm_op = "X86ISA::Imm8Op"
class MediaOpMeta(type):
def buildCppClasses(self, name, Name, suffix, code):
def buildCppClasses(self, name, Name, suffix, code, operands):
# Globals to stick the output in
global header_output
global decoder_output
global exec_output
imm_operands = list([op if op != 'op2' else imm_op for
op in operands])
operands = list([op if op != 'op2' else fp_src2_op for
op in operands])
# If op2 is used anywhere, make register and immediate versions
# of this code.
matcher = re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?")
matcher = \
re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?")
match = matcher.search(code)
if match:
typeQual = ""
@@ -142,22 +109,13 @@ let {{
typeQual = match.group("typeQual")
src2_name = "%sFpSrcReg2%s" % (match.group("prefix"), typeQual)
self.buildCppClasses(name, Name, suffix,
matcher.sub(src2_name, code))
matcher.sub(src2_name, code), operands)
self.buildCppClasses(name + "i", Name, suffix + "Imm",
matcher.sub("imm8", code))
matcher.sub("imm8", code), imm_operands)
return
base = "X86ISA::MediaOp"
# If imm8 shows up in the code, use the immediate templates, if
# not, hopefully the register ones will be correct.
matcher = re.compile("(?<!\w)imm8(?!\w)")
if matcher.search(code):
base += "Imm"
templates = immTemplates
else:
base += "Reg"
templates = regTemplates
base = "X86ISA::InstOperands<" + \
", ".join(["X86ISA::MediaOpBase"] + operands) + ">"
# Get everything ready for the substitution
opt_args = []
@@ -167,9 +125,8 @@ let {{
opt_args)
# Generate the actual code (finally!)
header_output += templates[0].subst(iop)
decoder_output += templates[1].subst(iop)
exec_output += templates[2].subst(iop)
header_output += MediaOpDeclare.subst(iop)
exec_output += MediaOpExecute.subst(iop)
def __new__(mcls, Name, bases, dict):
@@ -186,9 +143,10 @@ let {{
cls.className = Name
cls.base_mnemonic = name
code = cls.code
operands = cls.operands
# Set up the C++ classes
mcls.buildCppClasses(cls, name, Name, "", code)
mcls.buildCppClasses(cls, name, Name, "", code, operands)
# Hook into the microassembler dict
global microopClasses
@@ -206,11 +164,11 @@ let {{
# This class itself doesn't act as a microop
abstract = True
def __init__(self, dest, src1, op2,
size = None, destSize = None, srcSize = None, ext = None):
self.dest = dest
self.src1 = src1
self.op2 = op2
def __init__(self, *args, size=None, destSize=None, srcSize=None,
ext=None):
self.args = list(map(str, args))
self.srcSize = None
self.destSize = None
if size is not None:
self.srcSize = size
self.destSize = size
@@ -231,23 +189,40 @@ let {{
className = self.className
if self.mnemonic == self.base_mnemonic + 'i':
className += "Imm"
ext_args = [str(self.ext)] + self.args
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(src1)s, %(op2)s, %(dest)s,
%(srcSize)s, %(destSize)s, %(ext)s)''' % {
%(flags)s, %(srcSize)s, %(destSize)s, %(ext_args)s)
''' % {
"class_name" : className,
"flags" : self.microFlagsText(microFlags),
"src1" : self.src1, "op2" : self.op2,
"dest" : self.dest,
"srcSize" : self.srcSize,
"destSize" : self.destSize,
"ext" : self.ext}
"ext_args" : ", ".join(ext_args)
}
return allocator
class Mov2int(MediaOp):
def __init__(self, dest, src1, src2 = 0, \
size = None, destSize = None, srcSize = None, ext = None):
super(Mov2int, self).__init__(dest, src1,\
src2, size, destSize, srcSize, ext)
class Media0Op(MediaOp):
abstract = True
operands = ()
def __init__(self, **kwargs):
super(Media0Op, self).__init__(**kwargs)
class Media2Op(MediaOp):
abstract = True
operands = (fp_dest_op, fp_src1_op)
def __init__(self, op1, op2, **kwargs):
super(Media2Op, self).__init__(op1, op2, **kwargs)
class Media3Op(MediaOp):
abstract = True
operands = (fp_dest_op, fp_src1_op, fp_src2_op)
def __init__(self, op1, op2, op3, **kwargs):
super(Media3Op, self).__init__(op1, op2, op3, **kwargs)
class Mov2int(Media3Op):
def __init__(self, dest, src1, src2=0, **kwargs):
super(Mov2int, self).__init__(dest, src1, src2, **kwargs)
operands = (int_dest_op, fp_src1_op, imm_op)
op_class = 'SimdMiscOp'
code = '''
int items = sizeof(double) / srcSize;
@@ -265,11 +240,10 @@ let {{
}
'''
class Mov2fp(MediaOp):
def __init__(self, dest, src1, src2 = 0, \
size = None, destSize = None, srcSize = None, ext = None):
super(Mov2fp, self).__init__(dest, src1,\
src2, size, destSize, srcSize, ext)
class Mov2fp(Media3Op):
def __init__(self, dest, src1, src2=0, **kwargs):
super(Mov2fp, self).__init__(dest, src1, src2, **kwargs)
operands = (fp_dest_op, int_src1_op, imm_op)
op_class = 'SimdMiscOp'
code = '''
int items = sizeof(double) / destSize;
@@ -287,11 +261,8 @@ let {{
}
'''
class Movsign(MediaOp):
def __init__(self, dest, src, \
size = None, destSize = None, srcSize = None, ext = None):
super(Movsign, self).__init__(dest, src,\
"InstRegIndex(0)", size, destSize, srcSize, ext)
class Movsign(Media2Op):
operands = (int_dest_op, fp_src1_op)
op_class = 'SimdMiscOp'
code = '''
int items = sizeof(double) / srcSize;
@@ -305,7 +276,7 @@ let {{
DestReg = DestReg | result;
'''
class Maskmov(MediaOp):
class Maskmov(Media3Op):
op_class = 'SimdMiscOp'
code = '''
assert(srcSize == destSize);
@@ -324,7 +295,7 @@ let {{
FpDestReg_uqw = result;
'''
class shuffle(MediaOp):
class shuffle(Media3Op):
op_class = 'SimdMiscOp'
code = '''
assert(srcSize == destSize);
@@ -376,7 +347,7 @@ let {{
FpDestReg_uqw = result;
'''
class Unpack(MediaOp):
class Unpack(Media3Op):
op_class = 'SimdMiscOp'
code = '''
assert(srcSize == destSize);
@@ -403,7 +374,7 @@ let {{
FpDestReg_uqw = result;
'''
class Pack(MediaOp):
class Pack(Media3Op):
op_class = 'SimdMiscOp'
code = '''
assert(srcSize == destSize * 2);
@@ -471,39 +442,39 @@ let {{
FpDestReg_uqw = result;
'''
class Mxor(MediaOp):
class Mxor(Media3Op):
def __init__(self, dest, src1, src2):
super(Mxor, self).__init__(dest, src1, src2, 1)
super(Mxor, self).__init__(dest, src1, src2, size=1)
op_class = 'SimdAluOp'
code = '''
FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;
'''
class Mor(MediaOp):
class Mor(Media3Op):
def __init__(self, dest, src1, src2):
super(Mor, self).__init__(dest, src1, src2, 1)
super(Mor, self).__init__(dest, src1, src2, size=1)
op_class = 'SimdAluOp'
code = '''
FpDestReg_uqw = FpSrcReg1_uqw | FpSrcReg2_uqw;
'''
class Mand(MediaOp):
class Mand(Media3Op):
def __init__(self, dest, src1, src2):
super(Mand, self).__init__(dest, src1, src2, 1)
super(Mand, self).__init__(dest, src1, src2, size=1)
op_class = 'SimdAluOp'
code = '''
FpDestReg_uqw = FpSrcReg1_uqw & FpSrcReg2_uqw;
'''
class Mandn(MediaOp):
class Mandn(Media3Op):
def __init__(self, dest, src1, src2):
super(Mandn, self).__init__(dest, src1, src2, 1)
super(Mandn, self).__init__(dest, src1, src2, size=1)
op_class = 'SimdAluOp'
code = '''
FpDestReg_uqw = ~FpSrcReg1_uqw & FpSrcReg2_uqw;
'''
class Mminf(MediaOp):
class Mminf(Media3Op):
op_class = 'SimdFloatCmpOp'
code = '''
union floatInt
@@ -554,7 +525,7 @@ let {{
FpDestReg_uqw = result;
'''
class Mmaxf(MediaOp):
class Mmaxf(Media3Op):
op_class = 'SimdFloatCmpOp'
code = '''
union floatInt
@@ -605,7 +576,7 @@ let {{
FpDestReg_uqw = result;
'''
class Mmini(MediaOp):
class Mmini(Media3Op):
op_class = 'SimdCmpOp'
code = '''
@@ -644,7 +615,7 @@ let {{
FpDestReg_uqw = result;
'''
class Mmaxi(MediaOp):
class Mmaxi(Media3Op):
op_class = 'SimdCmpOp'
code = '''
@@ -683,12 +654,8 @@ let {{
FpDestReg_uqw = result;
'''
class Msqrt(MediaOp):
class Msqrt(Media2Op):
op_class = 'SimdFloatSqrtOp'
def __init__(self, dest, src, \
size = None, destSize = None, srcSize = None, ext = None):
super(Msqrt, self).__init__(dest, src,\
"InstRegIndex(0)", size, destSize, srcSize, ext)
code = '''
union floatInt
{
@@ -730,11 +697,7 @@ let {{
'''
# compute approximate reciprocal --- single-precision only
class Mrcp(MediaOp):
def __init__(self, dest, src, \
size = None, destSize = None, srcSize = None, ext = None):
super(Mrcp, self).__init__(dest, src,\
"InstRegIndex(0)", size, destSize, srcSize, ext)
class Mrcp(Media2Op):
op_class = 'SimdFloatAluOp'
code = '''
union floatInt
@@ -765,7 +728,7 @@ let {{
FpDestReg_uqw = result;
'''
class Maddf(MediaOp):
class Maddf(Media3Op):
op_class = 'SimdFloatAddOp'
code = '''
union floatInt
@@ -812,7 +775,7 @@ let {{
FpDestReg_uqw = result;
'''
class Msubf(MediaOp):
class Msubf(Media3Op):
op_class = 'SimdFloatAddOp'
code = '''
union floatInt
@@ -859,7 +822,7 @@ let {{
FpDestReg_uqw = result;
'''
class Mmulf(MediaOp):
class Mmulf(Media3Op):
op_class = 'SimdFloatMultOp'
code = '''
union floatInt
@@ -906,7 +869,7 @@ let {{
FpDestReg_uqw = result;
'''
class Mdivf(MediaOp):
class Mdivf(Media3Op):
op_class = 'SimdFloatDivOp'
code = '''
union floatInt
@@ -953,7 +916,7 @@ let {{
FpDestReg_uqw = result;
'''
class Maddi(MediaOp):
class Maddi(Media3Op):
op_class = 'SimdAddOp'
code = '''
assert(srcSize == destSize);
@@ -991,7 +954,7 @@ let {{
FpDestReg_uqw = result;
'''
class Msubi(MediaOp):
class Msubi(Media3Op):
op_class = 'SimdAddOp'
code = '''
assert(srcSize == destSize);
@@ -1033,7 +996,7 @@ let {{
FpDestReg_uqw = result;
'''
class Mmuli(MediaOp):
class Mmuli(Media3Op):
op_class = 'SimdMultOp'
code = '''
int srcBits = srcSize * 8;
@@ -1080,7 +1043,7 @@ let {{
FpDestReg_uqw = result;
'''
class Mavg(MediaOp):
class Mavg(Media3Op):
op_class = 'SimdAddOp'
code = '''
assert(srcSize == destSize);
@@ -1101,7 +1064,7 @@ let {{
FpDestReg_uqw = result;
'''
class Msad(MediaOp):
class Msad(Media3Op):
op_class = 'SimdAddOp'
code = '''
int srcBits = srcSize * 8;
@@ -1121,7 +1084,8 @@ let {{
FpDestReg_uqw = sum & mask(destSize * 8);
'''
class Msrl(MediaOp):
class Msrl(Media3Op):
operands = (fp_dest_op, fp_src1_op, 'op2')
op_class = 'SimdShiftOp'
code = '''
@@ -1149,7 +1113,8 @@ let {{
FpDestReg_uqw = result;
'''
class Msra(MediaOp):
class Msra(Media3Op):
operands = (fp_dest_op, fp_src1_op, 'op2')
op_class = 'SimdShiftOp'
code = '''
@@ -1181,7 +1146,8 @@ let {{
FpDestReg_uqw = result;
'''
class Msll(MediaOp):
class Msll(Media3Op):
operands = (fp_dest_op, fp_src1_op, 'op2')
op_class = 'SimdShiftOp'
code = '''
@@ -1208,11 +1174,7 @@ let {{
FpDestReg_uqw = result;
'''
class Cvtf2i(MediaOp):
def __init__(self, dest, src, \
size = None, destSize = None, srcSize = None, ext = None):
super(Cvtf2i, self).__init__(dest, src,\
"InstRegIndex(0)", size, destSize, srcSize, ext)
class Cvtf2i(Media2Op):
op_class = 'SimdFloatCvtOp'
code = '''
union floatInt
@@ -1283,11 +1245,7 @@ let {{
FpDestReg_uqw = result;
'''
class Cvti2f(MediaOp):
def __init__(self, dest, src, \
size = None, destSize = None, srcSize = None, ext = None):
super(Cvti2f, self).__init__(dest, src,\
"InstRegIndex(0)", size, destSize, srcSize, ext)
class Cvti2f(Media2Op):
op_class = 'SimdFloatCvtOp'
code = '''
union floatInt
@@ -1346,11 +1304,7 @@ let {{
FpDestReg_uqw = result;
'''
class Cvtf2f(MediaOp):
def __init__(self, dest, src, \
size = None, destSize = None, srcSize = None, ext = None):
super(Cvtf2f, self).__init__(dest, src,\
"InstRegIndex(0)", size, destSize, srcSize, ext)
class Cvtf2f(Media2Op):
op_class = 'SimdFloatCvtOp'
code = '''
union floatInt
@@ -1415,7 +1369,7 @@ let {{
FpDestReg_uqw = result;
'''
class Mcmpi2r(MediaOp):
class Mcmpi2r(Media3Op):
op_class = 'SimdCvtOp'
code = '''
union floatInt
@@ -1455,7 +1409,7 @@ let {{
FpDestReg_uqw = result;
'''
class Mcmpf2r(MediaOp):
class Mcmpf2r(Media3Op):
op_class = 'SimdFloatCvtOp'
code = '''
union floatInt
@@ -1538,11 +1492,8 @@ let {{
FpDestReg_uqw = result;
'''
class Mcmpf2rf(MediaOp):
def __init__(self, src1, src2,\
size = None, destSize = None, srcSize = None, ext = None):
super(Mcmpf2rf, self).__init__("InstRegIndex(0)", src1,\
src2, size, destSize, srcSize, ext)
class Mcmpf2rf(Media2Op):
operands = (fp_src1_op, fp_src2_op)
op_class = 'SimdFloatCvtOp'
code = '''
union floatInt
@@ -1597,10 +1548,9 @@ let {{
ccFlagBits = ccFlagBits | ZFBit;
'''
class Emms(MediaOp):
op_class = 'FloatMiscOp'
class Emms(Media0Op):
def __init__(self):
super(Emms, self).__init__('InstRegIndex(MISCREG_FTW)',
'InstRegIndex(0)', 'InstRegIndex(0)', 2)
super(Emms, self).__init__(size=2)
op_class = 'FloatMiscOp'
code = 'FTW = 0xFFFF;'
}};

230
src/arch/x86/isa/microops/regop.isa
View File

@@ -294,15 +294,15 @@ let {{
prefix = ""
for (rex, decl) in (
("(?<!\w)psrc1(?!\w)",
"uint64_t psrc1 = pick(SSrcReg1, 0, dataSize);"),
"uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"),
("(?<!\w)psrc2(?!\w)",
"uint64_t psrc2 = pick(SSrcReg2, 1, dataSize);"),
"uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"),
("(?<!\w)spsrc1(?!\w)",
"int64_t spsrc1 = "
"signedPick(SSrcReg1, 0, dataSize);"),
"signedPick(SrcReg1, 0, dataSize);"),
("(?<!\w)spsrc2(?!\w)",
"int64_t spsrc2 = "
"signedPick(SSrcReg2, 1, dataSize);"),
"signedPick(SrcReg2, 1, dataSize);"),
("(?<!\w)simm8(?!\w)",
"int8_t simm8 = imm8;")):
matcher = re.compile(rex)
@@ -528,59 +528,59 @@ let {{
class Add(FlagRegOp):
code = '''
result = psrc1 + op2;
SDestReg = merge(SDestReg, result, dataSize);
DestReg = merge(DestReg, result, dataSize);
'''
big_code = 'SDestReg = result = (psrc1 + op2) & mask(dataSize * 8);'
big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);'
class Or(LogicRegOp):
code = '''
result = psrc1 | op2;
SDestReg = merge(SDestReg, result, dataSize);
DestReg = merge(DestReg, result, dataSize);
'''
big_code = 'SDestReg = result = (psrc1 | op2) & mask(dataSize * 8);'
big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);'
class Adc(FlagRegOp):
code = '''
CCFlagBits flags = cfofBits;
result = psrc1 + op2 + flags.cf;
SDestReg = merge(SDestReg, result, dataSize);
DestReg = merge(DestReg, result, dataSize);
'''
big_code = '''
CCFlagBits flags = cfofBits;
SDestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
'''
class Sbb(SubRegOp):
code = '''
CCFlagBits flags = cfofBits;
result = psrc1 - op2 - flags.cf;
SDestReg = merge(SDestReg, result, dataSize);
DestReg = merge(DestReg, result, dataSize);
'''
big_code = '''
CCFlagBits flags = cfofBits;
SDestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
'''
class And(LogicRegOp):
code = '''
result = psrc1 & op2;
SDestReg = merge(SDestReg, result, dataSize)
DestReg = merge(DestReg, result, dataSize)
'''
big_code = 'SDestReg = result = (psrc1 & op2) & mask(dataSize * 8)'
big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)'
class Sub(SubRegOp):
code = '''
result = psrc1 - op2;
DestReg = merge(SDestReg, result, dataSize)
DestReg = merge(DestReg, result, dataSize)
'''
big_code = 'SDestReg = result = (psrc1 - op2) & mask(dataSize * 8)'
big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)'
class Xor(LogicRegOp):
code = '''
result = psrc1 ^ op2;
SDestReg = merge(SDestReg, result, dataSize)
DestReg = merge(DestReg, result, dataSize)
'''
big_code = 'SDestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)'
big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)'
class Mul1s(WrRegOp):
op_class = 'IntMultOp'
@@ -676,8 +676,8 @@ let {{
'''
class Mulel(RdRegOp):
code = 'SDestReg = merge(SSrcReg1, ProdLow, dataSize);'
big_code = 'SDestReg = ProdLow & mask(dataSize * 8);'
code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
big_code = 'DestReg = ProdLow & mask(dataSize * 8);'
class Muleh(RdRegOp):
def __init__(self, dest, src1=None, flags=None,
@@ -685,8 +685,8 @@ let {{
if not src1:
src1 = dest
super(RdRegOp, self).__init__(dest, src1, dataSize=dataSize)
code = 'SDestReg = merge(SSrcReg1, ProdHi, dataSize);'
big_code = 'SDestReg = ProdHi & mask(dataSize * 8);'
code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
big_code = 'DestReg = ProdHi & mask(dataSize * 8);'
# One or two bit divide
class Div1(WrRegOp):
@@ -732,7 +732,7 @@ let {{
if (divisor & (1ULL << 63)) {
while (remaining && !(dividend & (1ULL << 63))) {
dividend = (dividend << 1) |
bits(SSrcReg1, remaining - 1);
bits(SrcReg1, remaining - 1);
quotient <<= 1;
remaining--;
}
@@ -741,7 +741,7 @@ let {{
if (dividend < divisor && remaining) {
highBit = true;
dividend = (dividend << 1) |
bits(SSrcReg1, remaining - 1);
bits(SrcReg1, remaining - 1);
quotient <<= 1;
remaining--;
}
@@ -755,7 +755,7 @@ let {{
//Shift in bits from the low order portion of the dividend
while (dividend < divisor && remaining) {
dividend = (dividend << 1) |
bits(SSrcReg1, remaining - 1);
bits(SrcReg1, remaining - 1);
quotient <<= 1;
remaining--;
}
@@ -770,8 +770,8 @@ let {{
Remainder = remainder;
Quotient = quotient;
'''
code = divCode % "SDestReg = merge(SDestReg, remaining, dataSize);"
big_code = divCode % "SDestReg = remaining & mask(dataSize * 8);"
code = divCode % "DestReg = merge(DestReg, remaining, dataSize);"
big_code = divCode % "DestReg = remaining & mask(dataSize * 8);"
flag_code = '''
if (remaining == 0)
PredezfBit = PredezfBit | (ext & EZFBit);
@@ -780,27 +780,27 @@ let {{
'''
class Divq(RdRegOp):
code = 'SDestReg = merge(SSrcReg1, Quotient, dataSize);'
big_code = 'SDestReg = Quotient & mask(dataSize * 8);'
code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
big_code = 'DestReg = Quotient & mask(dataSize * 8);'
class Divr(RdRegOp):
code = 'SDestReg = merge(SSrcReg1, Remainder, dataSize);'
big_code = 'SDestReg = Remainder & mask(dataSize * 8);'
code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
big_code = 'DestReg = Remainder & mask(dataSize * 8);'
class Mov(BasicRegOp, CondRegOp):
code = 'SDestReg = merge(SSrcReg1, op2, dataSize)'
else_code = 'SDestReg = SDestReg;'
code = 'DestReg = merge(SrcReg1, op2, dataSize)'
else_code = 'DestReg = DestReg;'
# Shift instructions
class Sll(BasicRegOp):
code = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
SDestReg = merge(SDestReg, psrc1 << shiftAmt, dataSize);
DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
'''
big_code = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
SDestReg = (psrc1 << shiftAmt) & mask(dataSize * 8);
DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8);
'''
flag_code = '''
// If the shift amount is zero, no flags should be modified.
@@ -813,7 +813,7 @@ let {{
int CFBits = 0;
//Figure out if we -would- set the CF bits if requested.
if (shiftAmt <= dataSize * 8 &&
bits(SSrcReg1, dataSize * 8 - shiftAmt)) {
bits(SrcReg1, dataSize * 8 - shiftAmt)) {
CFBits = 1;
}
@@ -825,14 +825,14 @@ let {{
//Figure out what the OF bit should be.
if ((ext & OFBit) &&
(CFBits ^ bits(SDestReg, dataSize * 8 - 1))) {
(CFBits ^ bits(DestReg, dataSize * 8 - 1))) {
PredcfofBits = PredcfofBits | OFBit;
}
//Use the regular mechanisms to calculate the other flags.
uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
SDestReg, psrc1, op2);
DestReg, psrc1, op2);
PredezfBit = newFlags & EZFBit;
PreddfBit = newFlags & DFBit;
@@ -847,13 +847,13 @@ let {{
code = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
SDestReg = merge(SDestReg, (psrc1 >> shiftAmt) & logicalMask,
DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask,
dataSize);
'''
big_code = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
SDestReg = (psrc1 >> shiftAmt) & logicalMask;
DestReg = (psrc1 >> shiftAmt) & logicalMask;
'''
flag_code = '''
// If the shift amount is zero, no flags should be modified.
@@ -866,19 +866,19 @@ let {{
//If some combination of the CF bits need to be set, set them.
if ((ext & (CFBit | ECFBit)) &&
shiftAmt <= dataSize * 8 &&
bits(SSrcReg1, shiftAmt - 1)) {
bits(SrcReg1, shiftAmt - 1)) {
PredcfofBits = PredcfofBits | (ext & CFBit);
PredecfBit = PredecfBit | (ext & ECFBit);
}
//Figure out what the OF bit should be.
if ((ext & OFBit) && bits(SSrcReg1, dataSize * 8 - 1))
if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
PredcfofBits = PredcfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
SDestReg, psrc1, op2);
DestReg, psrc1, op2);
PredezfBit = newFlags & EZFBit;
PreddfBit = newFlags & DFBit;
@@ -894,14 +894,14 @@ let {{
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint64_t arithMask = (shiftAmt == 0) ? 0 :
-bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
SDestReg = merge(SDestReg,
DestReg = merge(DestReg,
(psrc1 >> shiftAmt) | arithMask, dataSize);
'''
big_code = '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
uint64_t arithMask = (shiftAmt == 0) ? 0 :
-bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
SDestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8);
DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8);
'''
flag_code = '''
// If the shift amount is zero, no flags should be modified.
@@ -915,7 +915,7 @@ let {{
uint8_t effectiveShift =
(shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
if ((ext & (CFBit | ECFBit)) &&
bits(SSrcReg1, effectiveShift - 1)) {
bits(SrcReg1, effectiveShift - 1)) {
PredcfofBits = PredcfofBits | (ext & CFBit);
PredecfBit = PredecfBit | (ext & ECFBit);
}
@@ -923,7 +923,7 @@ let {{
//Use the regular mechanisms to calculate the other flags.
uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
SDestReg, psrc1, op2);
DestReg, psrc1, op2);
PredezfBit = newFlags & EZFBit;
PreddfBit = newFlags & DFBit;
@@ -939,9 +939,9 @@ let {{
if (realShiftAmt) {
uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
SDestReg = merge(SDestReg, top | bottom, dataSize);
DestReg = merge(DestReg, top | bottom, dataSize);
} else
SDestReg = merge(SDestReg, SDestReg, dataSize);
DestReg = merge(DestReg, DestReg, dataSize);
'''
flag_code = '''
// If the shift amount is zero, no flags should be modified.
@@ -952,8 +952,8 @@ let {{
PredecfBit = PredecfBit & ~(ext & ECFBit);
//Find the most and second most significant bits of the result.
int msb = bits(SDestReg, dataSize * 8 - 1);
int smsb = bits(SDestReg, dataSize * 8 - 2);
int msb = bits(DestReg, dataSize * 8 - 1);
int smsb = bits(DestReg, dataSize * 8 - 2);
//If some combination of the CF bits need to be set, set them.
if ((ext & (CFBit | ECFBit)) && msb) {
PredcfofBits = PredcfofBits | (ext & CFBit);
@@ -967,7 +967,7 @@ let {{
//Use the regular mechanisms to calculate the other flags.
uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
SDestReg, psrc1, op2);
DestReg, psrc1, op2);
PredezfBit = newFlags & EZFBit;
PreddfBit = newFlags & DFBit;
@@ -986,9 +986,9 @@ let {{
if (realShiftAmt > 1)
top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
SDestReg = merge(SDestReg, top | bottom, dataSize);
DestReg = merge(DestReg, top | bottom, dataSize);
} else
SDestReg = merge(SDestReg, SDestReg, dataSize);
DestReg = merge(DestReg, DestReg, dataSize);
'''
flag_code = '''
// If the shift amount is zero, no flags should be modified.
@@ -1001,13 +1001,13 @@ let {{
//Figure out what the OF bit should be.
if ((ext & OFBit) && (origCFBit ^
bits(SSrcReg1, dataSize * 8 - 1))) {
bits(SrcReg1, dataSize * 8 - 1))) {
PredcfofBits = PredcfofBits | OFBit;
}
//If some combination of the CF bits need to be set, set them.
if ((ext & (CFBit | ECFBit)) &&
(realShiftAmt == 0) ? origCFBit :
bits(SSrcReg1, realShiftAmt - 1)) {
bits(SrcReg1, realShiftAmt - 1)) {
PredcfofBits = PredcfofBits | (ext & CFBit);
PredecfBit = PredecfBit | (ext & ECFBit);
}
@@ -1015,7 +1015,7 @@ let {{
//Use the regular mechanisms to calculate the other flags.
uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
SDestReg, psrc1, op2);
DestReg, psrc1, op2);
PredezfBit = newFlags & EZFBit;
PreddfBit = newFlags & DFBit;
@@ -1032,9 +1032,9 @@ let {{
uint64_t top = psrc1 << realShiftAmt;
uint64_t bottom =
bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
SDestReg = merge(SDestReg, top | bottom, dataSize);
DestReg = merge(DestReg, top | bottom, dataSize);
} else
SDestReg = merge(SDestReg, SDestReg, dataSize);
DestReg = merge(DestReg, DestReg, dataSize);
'''
flag_code = '''
// If the shift amount is zero, no flags should be modified.
@@ -1045,8 +1045,8 @@ let {{
PredecfBit = PredecfBit & ~(ext & ECFBit);
//The CF bits, if set, would be set to the lsb of the result.
int lsb = SDestReg & 0x1;
int msb = bits(SDestReg, dataSize * 8 - 1);
int lsb = DestReg & 0x1;
int msb = bits(DestReg, dataSize * 8 - 1);
//If some combination of the CF bits need to be set, set them.
if ((ext & (CFBit | ECFBit)) && lsb) {
PredcfofBits = PredcfofBits | (ext & CFBit);
@@ -1060,7 +1060,7 @@ let {{
//Use the regular mechanisms to calculate the other flags.
uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
SDestReg, psrc1, op2);
DestReg, psrc1, op2);
PredezfBit = newFlags & EZFBit;
PreddfBit = newFlags & DFBit;
@@ -1081,9 +1081,9 @@ let {{
bottom |=
bits(psrc1, dataSize * 8 - 1,
dataSize * 8 - realShiftAmt + 1);
SDestReg = merge(SDestReg, top | bottom, dataSize);
DestReg = merge(DestReg, top | bottom, dataSize);
} else
SDestReg = merge(SDestReg, SDestReg, dataSize);
DestReg = merge(DestReg, DestReg, dataSize);
'''
flag_code = '''
// If the shift amount is zero, no flags should be modified.
@@ -1094,8 +1094,8 @@ let {{
PredcfofBits = PredcfofBits & ~(ext & (CFBit | OFBit));
PredecfBit = PredecfBit & ~(ext & ECFBit);
int msb = bits(SDestReg, dataSize * 8 - 1);
int CFBits = bits(SSrcReg1, dataSize * 8 - realShiftAmt);
int msb = bits(DestReg, dataSize * 8 - 1);
int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
//If some combination of the CF bits need to be set, set them.
if ((ext & (CFBit | ECFBit)) &&
(realShiftAmt == 0) ? origCFBit : CFBits) {
@@ -1110,7 +1110,7 @@ let {{
//Use the regular mechanisms to calculate the other flags.
uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
SDestReg, psrc1, op2);
DestReg, psrc1, op2);
PredezfBit = newFlags & EZFBit;
PreddfBit = newFlags & DFBit;
@@ -1135,8 +1135,8 @@ let {{
}
%s
'''
code = sldCode % "SDestReg = merge(SDestReg, result, dataSize);"
big_code = sldCode % "SDestReg = result & mask(dataSize * 8);"
code = sldCode % "DestReg = merge(DestReg, result, dataSize);"
big_code = sldCode % "DestReg = result & mask(dataSize * 8);"
flag_code = '''
// If the shift amount is zero, no flags should be modified.
if (shiftAmt) {
@@ -1150,7 +1150,7 @@ let {{
if ((realShiftAmt == 0 &&
bits(DoubleBits, 0)) ||
(realShiftAmt <= dataBits &&
bits(SSrcReg1, dataBits - realShiftAmt)) ||
bits(SrcReg1, dataBits - realShiftAmt)) ||
(realShiftAmt > dataBits &&
bits(DoubleBits, 2 * dataBits - realShiftAmt))) {
CFBits = 1;
@@ -1163,14 +1163,14 @@ let {{
}
//Figure out what the OF bit should be.
if ((ext & OFBit) && (bits(SSrcReg1, dataBits - 1) ^
if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
bits(result, dataBits - 1)))
PredcfofBits = PredcfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
SDestReg, psrc1, op2);
DestReg, psrc1, op2);
PredezfBit = newFlags & EZFBit;
PreddfBit = newFlags & DFBit;
@@ -1201,8 +1201,8 @@ let {{
}
%s
'''
code = srdCode % "SDestReg = merge(SDestReg, result, dataSize);"
big_code = srdCode % "SDestReg = result & mask(dataSize * 8);"
code = srdCode % "DestReg = merge(DestReg, result, dataSize);"
big_code = srdCode % "DestReg = result & mask(dataSize * 8);"
flag_code = '''
// If the shift amount is zero, no flags should be modified.
if (shiftAmt) {
@@ -1216,7 +1216,7 @@ let {{
if ((realShiftAmt == 0 &&
bits(DoubleBits, dataBits - 1)) ||
(realShiftAmt <= dataBits &&
bits(SSrcReg1, realShiftAmt - 1)) ||
bits(SrcReg1, realShiftAmt - 1)) ||
(realShiftAmt > dataBits &&
bits(DoubleBits, realShiftAmt - dataBits - 1))) {
CFBits = 1;
@@ -1229,14 +1229,14 @@ let {{
}
//Figure out what the OF bit should be.
if ((ext & OFBit) && (bits(SSrcReg1, dataBits - 1) ^
if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
bits(result, dataBits - 1)))
PredcfofBits = PredcfofBits | OFBit;
//Use the regular mechanisms to calculate the other flags.
uint64_t newFlags = genFlags(PredccFlagBits | PreddfBit |
PredezfBit, ext & ~(CFBit | ECFBit | OFBit),
SDestReg, psrc1, op2);
DestReg, psrc1, op2);
PredezfBit = newFlags & EZFBit;
PreddfBit = newFlags & DFBit;
@@ -1278,14 +1278,14 @@ let {{
'''
class Rdip(RdRegOp):
code = 'SDestReg = NRIP - CSBase;'
code = 'DestReg = NRIP - CSBase;'
class Ruflags(RdRegOp):
code = 'SDestReg = ccFlagBits | cfofBits | dfBit | ecfBit | ezfBit;'
code = 'DestReg = ccFlagBits | cfofBits | dfBit | ecfBit | ezfBit;'
class Rflags(RdRegOp):
code = '''
SDestReg = ccFlagBits | cfofBits | dfBit |
DestReg = ccFlagBits | cfofBits | dfBit |
ecfBit | ezfBit | nccFlagBits;
'''
@@ -1293,14 +1293,14 @@ let {{
code = '''
int flag = bits(ccFlagBits | cfofBits | dfBit |
ecfBit | ezfBit, imm8);
SDestReg = merge(SDestReg, flag, dataSize);
DestReg = merge(DestReg, flag, dataSize);
ezfBit = (flag == 0) ? EZFBit : 0;
'''
big_code = '''
int flag = bits(ccFlagBits | cfofBits | dfBit |
ecfBit | ezfBit, imm8);
SDestReg = flag & mask(dataSize * 8);
DestReg = flag & mask(dataSize * 8);
ezfBit = (flag == 0) ? EZFBit : 0;
'''
@@ -1317,7 +1317,7 @@ let {{
ecfBit | ezfBit) & flagMask;
int flag = bits(flags, imm8);
SDestReg = merge(SDestReg, flag, dataSize);
DestReg = merge(DestReg, flag, dataSize);
ezfBit = (flag == 0) ? EZFBit : 0;
'''
@@ -1327,7 +1327,7 @@ let {{
ecfBit | ezfBit) & flagMask;
int flag = bits(flags, imm8);
SDestReg = flag & mask(dataSize * 8);
DestReg = flag & mask(dataSize * 8);
ezfBit = (flag == 0) ? EZFBit : 0;
'''
@@ -1344,7 +1344,7 @@ let {{
int sign_bit = bits(val, bitPos, bitPos);
uint64_t maskVal = mask(bitPos+1);
val = sign_bit ? (val | ~maskVal) : (val & maskVal);
SDestReg = merge(SDestReg, val, dataSize);
DestReg = merge(DestReg, val, dataSize);
'''
big_code = '''
@@ -1354,7 +1354,7 @@ let {{
int sign_bit = bits(val, bitPos, bitPos);
uint64_t maskVal = mask(bitPos+1);
val = sign_bit ? (val | ~maskVal) : (val & maskVal);
SDestReg = val & mask(dataSize * 8);
DestReg = val & mask(dataSize * 8);
'''
flag_code = '''
@@ -1372,8 +1372,8 @@ let {{
'''
class Zext(BasicRegOp):
code = 'SDestReg = merge(SDestReg, bits(psrc1, op2, 0), dataSize);'
big_code = 'SDestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);'
code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);'
class Rddr(RegOp):
operands = (dest_op, dbg_src1_op)
@@ -1391,8 +1391,8 @@ let {{
%s
}
'''
code = rdrCode % "SDestReg = merge(SDestReg, DebugSrc1, dataSize);"
big_code = rdrCode % "SDestReg = DebugSrc1 & mask(dataSize * 8);"
code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);"
big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);"
class Wrdr(RegOp):
operands = (dbg_dest_op, src1_op)
@@ -1426,8 +1426,8 @@ let {{
%s
}
'''
code = rdcrCode % "SDestReg = merge(SDestReg, ControlSrc1, dataSize);"
big_code = rdcrCode % "SDestReg = ControlSrc1 & mask(dataSize * 8);"
code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);"
big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);"
class Wrcr(RegOp):
operands = (cr_dest_op, src1_op)
@@ -1518,20 +1518,20 @@ let {{
operands = (dest_op, seg_src1_op)
class Rdbase(RdSegOp):
code = 'SDestReg = merge(SDestReg, SegBaseSrc1, dataSize);'
big_code = 'SDestReg = SegBaseSrc1 & mask(dataSize * 8);'
code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);'
big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);'
class Rdlimit(RdSegOp):
code = 'SDestReg = merge(SDestReg, SegLimitSrc1, dataSize);'
big_code = 'SDestReg = SegLimitSrc1 & mask(dataSize * 8);'
code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);'
big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);'
class RdAttr(RdSegOp):
code = 'SDestReg = merge(SDestReg, SegAttrSrc1, dataSize);'
big_code = 'SDestReg = SegAttrSrc1 & mask(dataSize * 8);'
code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);'
big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);'
class Rdsel(RdSegOp):
code = 'SDestReg = merge(SDestReg, SegSelSrc1, dataSize);'
big_code = 'SDestReg = SegSelSrc1 & mask(dataSize * 8);'
code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);'
big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);'
class Rdval(RegOp):
operands = (dest_op, misc_src1_op)
@@ -1539,7 +1539,7 @@ let {{
super(Rdval, self).__init__(dest, src1, flags=flags,
dataSize=dataSize)
code = '''
SDestReg = MiscRegSrc1;
DestReg = MiscRegSrc1;
'''
class Wrval(RegOp):
@@ -1548,7 +1548,7 @@ let {{
super(Wrval, self).__init__(dest, src1, flags=flags,
dataSize=dataSize)
code = '''
MiscRegDest = SSrcReg1;
MiscRegDest = SrcReg1;
'''
class Chks(RegOp):
@@ -1559,8 +1559,8 @@ let {{
dataSize=dataSize)
code = '''
// The selector is in source 1 and can be at most 16 bits.
SegSelector selector = SSrcReg1;
SegDescriptor desc = SSrcReg2;
SegSelector selector = SrcReg1;
SegDescriptor desc = SrcReg2;
HandyM5Reg m5reg = M5Reg;
switch (imm8)
@@ -1677,9 +1677,9 @@ let {{
class Wrdh(BasicRegOp):
code = '''
SegDescriptor desc = SSrcReg1;
SegDescriptor desc = SrcReg1;
uint64_t target = bits(SSrcReg2, 31, 0) << 32;
uint64_t target = bits(SrcReg2, 31, 0) << 32;
switch(desc.type) {
case LDT64:
case AvailableTSS64:
@@ -1696,7 +1696,7 @@ let {{
fault = std::make_shared<GenericISA::M5PanicFault>(
"Wrdh used with wrong descriptor type!\\n");
}
SDestReg = target;
DestReg = target;
'''
class Wrtsc(WrRegOp):
@@ -1706,19 +1706,19 @@ let {{
class Rdtsc(RdRegOp):
code = '''
SDestReg = TscOp;
DestReg = TscOp;
'''
class Rdm5reg(RdRegOp):
code = '''
SDestReg = M5Reg;
DestReg = M5Reg;
'''
class Wrdl(BasicRegOp):
operands = (seg_dest_op, src1_op, 'op2')
code = '''
SegDescriptor desc = SSrcReg1;
SegSelector selector = SSrcReg2;
SegDescriptor desc = SrcReg1;
SegSelector selector = SrcReg2;
// This while loop is so we can use break statements in the code
// below to skip the rest of this section without a bunch of
// nesting.
@@ -1778,20 +1778,20 @@ let {{
super(Wrxftw, self).__init__(src1, flags=None, dataSize=dataSize)
code = '''
FTW = X86ISA::convX87XTagsToTags(SSrcReg1);
FTW = X86ISA::convX87XTagsToTags(SrcReg1);
'''
class Rdxftw(RdRegOp):
code = '''
SDestReg = X86ISA::convX87TagsToXTags(FTW);
DestReg = X86ISA::convX87TagsToXTags(FTW);
'''
class Popcnt(BasicRegOp):
code = 'SDestReg = merge(SDestReg, popCount(psrc1), dataSize);'
code = 'DestReg = merge(DestReg, popCount(psrc1), dataSize);'
flag_code = '''
ccFlagBits = ccFlagBits & ~(X86ISA::SFBit | X86ISA::AFBit |
X86ISA::ZFBit | X86ISA::PFBit);
if (findZero(dataSize * 8, SSrcReg1)) {
if (findZero(dataSize * 8, SrcReg1)) {
ccFlagBits = ccFlagBits | X86ISA::ZFBit;
}
cfofBits = cfofBits & ~(X86ISA::OFBit | X86ISA::CFBit);

13
src/arch/x86/isa/operands.isa
View File

@@ -54,10 +54,6 @@ def operand_types {{
}};
let {{
def foldInt(idx, foldBit, id):
return ('IntReg', 'uqw',
'X86ISA::INTREG_FOLDED(%s, %s)' % (idx, foldBit), 'IsInteger',
id)
def intReg(idx, id):
return ('IntReg', 'uqw', idx, 'IsInteger', id)
def impIntReg(idx, id):
@@ -89,14 +85,11 @@ let {{
}};
def operands {{
'SrcReg1': foldInt('src1', 'foldOBit', 1),
'SSrcReg1': intReg('src1', 1),
'SrcReg2': foldInt('src2', 'foldOBit', 2),
'SSrcReg2': intReg('src2', 2),
'SrcReg1': intReg('src1', 1),
'SrcReg2': intReg('src2', 2),
'Index': intReg('index', 3),
'Base': intReg('base', 4),
'DestReg': foldInt('dest', 'foldOBit', 5),
'SDestReg': intReg('dest', 5),
'DestReg': intReg('dest', 5),
'Data': intReg('data', 6),
'DataLow': intReg('dataLow', 6),
'DataHi': intReg('dataHi', 6),