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cpu-o3: Add missing tid in Rename's debug message

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These arguments were missing.

Change-Id: I8a76e46b2bcfc57f299145954fe72196f5969f29
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39075
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Daniel R. Carvalho
2021-01-13 23:55:40 -03:00
committed by Daniel Carvalho
parent d1933d9ce7
commit 3972d9dd93
1 changed files with 4 additions and 2 deletions
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6
src/cpu/o3/rename_impl.hh
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@@ -612,7 +612,8 @@ DefaultRename<Impl>::renameInsts(ThreadID tid)
if (inst->isLoad()) {
if (calcFreeLQEntries(tid) <= 0) {
DPRINTF(Rename, "[tid:%i] Cannot rename due to no free LQ\n");
DPRINTF(Rename, "[tid:%i] Cannot rename due to no free LQ\n",
tid);
source = LQ;
incrFullStat(source);
break;
@@ -621,7 +622,8 @@ DefaultRename<Impl>::renameInsts(ThreadID tid)
if (inst->isStore() || inst->isAtomic()) {
if (calcFreeSQEntries(tid) <= 0) {
DPRINTF(Rename, "[tid:%i] Cannot rename due to no free SQ\n");
DPRINTF(Rename, "[tid:%i] Cannot rename due to no free SQ\n",
tid);
source = SQ;
incrFullStat(source);
break;