SE/FS: Build/expose vport in SE mode.
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@@ -37,19 +37,18 @@ SimObject('MemObject.py')
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Source('bridge.cc')
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Source('bus.cc')
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Source('mem_object.cc')
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Source('mport.cc')
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Source('packet.cc')
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Source('port.cc')
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Source('tport.cc')
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Source('mport.cc')
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Source('vport.cc')
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if env['TARGET_ISA'] != 'no':
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SimObject('PhysicalMemory.py')
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Source('dram.cc')
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Source('physical.cc')
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if env['FULL_SYSTEM']:
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Source('vport.cc')
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elif env['TARGET_ISA'] != 'no':
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if not env['FULL_SYSTEM'] and env['TARGET_ISA'] != 'no':
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Source('page_table.cc')
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Source('translating_port.cc')
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