SE/FS: Build/expose vport in SE mode.
This commit is contained in:
@@ -96,15 +96,15 @@ class CheckerThreadContext : public ThreadContext
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TheISA::Kernel::Statistics *getKernelStats()
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{ return actualTC->getKernelStats(); }
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VirtualPort *getVirtPort()
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{ return actualTC->getVirtPort(); }
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#else
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TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
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Process *getProcessPtr() { return actualTC->getProcessPtr(); }
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#endif
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VirtualPort *getVirtPort()
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{ return actualTC->getVirtPort(); }
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FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
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Status status() const { return actualTC->status(); }
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@@ -37,14 +37,13 @@
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using namespace TheISA;
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#if FULL_SYSTEM
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VirtualPort *
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InOrderThreadContext::getVirtPort()
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{
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return thread->getVirtPort();
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}
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#if FULL_SYSTEM
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void
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InOrderThreadContext::dumpFuncProfile()
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@@ -118,8 +118,6 @@ class InOrderThreadContext : public ThreadContext
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TheISA::Kernel::Statistics *getKernelStats()
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{ return thread->kernelStats; }
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VirtualPort *getVirtPort();
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void connectMemPorts(ThreadContext *tc)
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{ thread->connectMemPorts(tc); }
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@@ -151,6 +149,7 @@ class InOrderThreadContext : public ThreadContext
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Process *getProcessPtr() { return thread->getProcessPtr(); }
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#endif
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VirtualPort *getVirtPort();
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FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
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/** Returns this thread's status. */
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@@ -97,8 +97,6 @@ class O3ThreadContext : public ThreadContext
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virtual TheISA::Kernel::Statistics *getKernelStats()
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{ return thread->kernelStats; }
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virtual VirtualPort *getVirtPort();
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virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
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#else
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virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
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@@ -107,6 +105,8 @@ class O3ThreadContext : public ThreadContext
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virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
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#endif
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virtual VirtualPort *getVirtPort();
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virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
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/** Returns this thread's status. */
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@@ -47,7 +47,6 @@
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#include "cpu/quiesce_event.hh"
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#include "debug/O3CPU.hh"
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#if FULL_SYSTEM
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template <class Impl>
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VirtualPort *
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O3ThreadContext<Impl>::getVirtPort()
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@@ -55,6 +54,7 @@ O3ThreadContext<Impl>::getVirtPort()
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return thread->getVirtPort();
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}
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#if FULL_SYSTEM
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template <class Impl>
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void
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O3ThreadContext<Impl>::dumpFuncProfile()
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@@ -123,15 +123,15 @@ class OzoneCPU : public BaseCPU
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TheISA::Kernel::Statistics *getKernelStats()
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{ return thread->getKernelStats(); }
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VirtualPort *getVirtPort()
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{ return thread->getVirtPort(); }
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#else
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TranslatingPort *getMemPort() { return thread->getMemPort(); }
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Process *getProcessPtr() { return thread->getProcessPtr(); }
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#endif
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VirtualPort *getVirtPort()
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{ return thread->getVirtPort(); }
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FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
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Status status() const { return thread->status(); }
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@@ -39,6 +39,7 @@
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#include "cpu/base.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "mem/vport.hh"
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#include "params/BaseCPU.hh"
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#if FULL_SYSTEM
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@@ -50,7 +51,6 @@
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#include "base/trace.hh"
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#include "cpu/profile.hh"
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#include "cpu/quiesce_event.hh"
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#include "mem/vport.hh"
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#include "sim/serialize.hh"
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#include "sim/sim_exit.hh"
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#else
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@@ -118,9 +118,7 @@ SimpleThread::SimpleThread()
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SimpleThread::~SimpleThread()
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{
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delete physPort;
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#if FULL_SYSTEM
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delete virtPort;
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#endif
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delete tc;
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}
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@@ -207,15 +207,13 @@ class SimpleThread : public ThreadState
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System *getSystemPtr() { return system; }
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#if FULL_SYSTEM
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FunctionalPort *getPhysPort() { return physPort; }
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/** Return a virtual port. This port cannot be cached locally in an object.
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* After a CPU switch it may point to the wrong memory object which could
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* mean stale data.
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*/
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VirtualPort *getVirtPort() { return virtPort; }
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#endif
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FunctionalPort *getPhysPort() { return physPort; }
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Status status() const { return _status; }
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@@ -128,8 +128,6 @@ class ThreadContext
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#if FULL_SYSTEM
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virtual TheISA::Kernel::Statistics *getKernelStats() = 0;
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virtual VirtualPort *getVirtPort() = 0;
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virtual void connectMemPorts(ThreadContext *tc) = 0;
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#else
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virtual TranslatingPort *getMemPort() = 0;
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@@ -137,6 +135,8 @@ class ThreadContext
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virtual Process *getProcessPtr() = 0;
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#endif
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virtual VirtualPort *getVirtPort() = 0;
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virtual FunctionalPort *getPhysPort() = 0;
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virtual Status status() const = 0;
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@@ -298,8 +298,6 @@ class ProxyThreadContext : public ThreadContext
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TheISA::Kernel::Statistics *getKernelStats()
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{ return actualTC->getKernelStats(); }
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VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
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void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
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#else
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TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
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@@ -307,6 +305,8 @@ class ProxyThreadContext : public ThreadContext
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Process *getProcessPtr() { return actualTC->getProcessPtr(); }
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#endif
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VirtualPort *getVirtPort() { return actualTC->getVirtPort(); }
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FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
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Status status() const { return actualTC->status(); }
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@@ -34,12 +34,12 @@
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#include "cpu/thread_state.hh"
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#include "mem/port.hh"
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#include "mem/translating_port.hh"
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#include "mem/vport.hh"
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#include "sim/serialize.hh"
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#if FULL_SYSTEM
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#include "arch/kernel_stats.hh"
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#include "cpu/quiesce_event.hh"
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#include "mem/vport.hh"
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#endif
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#if FULL_SYSTEM
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@@ -51,11 +51,11 @@ ThreadState::ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process)
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baseCpu(cpu), _threadId(_tid), lastActivate(0), lastSuspend(0),
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#if FULL_SYSTEM
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profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
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kernelStats(NULL), virtPort(NULL),
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kernelStats(NULL),
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#else
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port(NULL), process(_process),
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#endif
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physPort(NULL), funcExeInst(0), storeCondFailures(0)
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virtPort(NULL), physPort(NULL), funcExeInst(0), storeCondFailures(0)
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{
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}
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@@ -118,14 +118,6 @@ ThreadState::connectPhysPort()
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connectToMemFunc(physPort);
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}
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#if FULL_SYSTEM
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void
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ThreadState::connectMemPorts(ThreadContext *tc)
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{
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connectPhysPort();
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connectVirtPort(tc);
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}
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void
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ThreadState::connectVirtPort(ThreadContext *tc)
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{
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@@ -140,6 +132,14 @@ ThreadState::connectVirtPort(ThreadContext *tc)
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connectToMemFunc(virtPort);
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}
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#if FULL_SYSTEM
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void
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ThreadState::connectMemPorts(ThreadContext *tc)
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{
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connectPhysPort();
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connectVirtPort(tc);
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}
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void
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ThreadState::profileClear()
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{
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@@ -94,11 +94,11 @@ struct ThreadState {
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void connectPhysPort();
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void connectVirtPort(ThreadContext *tc);
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#if FULL_SYSTEM
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void connectMemPorts(ThreadContext *tc);
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void connectVirtPort(ThreadContext *tc);
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void dumpFuncProfile();
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EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
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@@ -108,8 +108,6 @@ struct ThreadState {
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void profileSample();
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TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
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VirtualPort *getVirtPort() { return virtPort; }
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#else
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Process *getProcessPtr() { return process; }
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@@ -118,6 +116,8 @@ struct ThreadState {
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void setMemPort(TranslatingPort *_port) { port = _port; }
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#endif
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VirtualPort *getVirtPort() { return virtPort; }
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FunctionalPort *getPhysPort() { return physPort; }
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void setPhysPort(FunctionalPort *port) { physPort = port; }
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@@ -186,15 +186,16 @@ struct ThreadState {
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TheISA::Kernel::Statistics *kernelStats;
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protected:
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/** A functional port, outgoing only, for functional accesse to virtual
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* addresses. */
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VirtualPort *virtPort;
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#else
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TranslatingPort *port;
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Process *process;
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#endif
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/** A functional port, outgoing only, for functional accesse to virtual
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* addresses. */
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VirtualPort *virtPort;
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/** A functional port outgoing only for functional accesses to physical
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* addresses.*/
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FunctionalPort *physPort;
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@@ -37,19 +37,18 @@ SimObject('MemObject.py')
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Source('bridge.cc')
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Source('bus.cc')
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Source('mem_object.cc')
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Source('mport.cc')
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Source('packet.cc')
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Source('port.cc')
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Source('tport.cc')
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Source('mport.cc')
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Source('vport.cc')
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if env['TARGET_ISA'] != 'no':
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SimObject('PhysicalMemory.py')
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Source('dram.cc')
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Source('physical.cc')
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if env['FULL_SYSTEM']:
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Source('vport.cc')
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elif env['TARGET_ISA'] != 'no':
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if not env['FULL_SYSTEM'] and env['TARGET_ISA'] != 'no':
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Source('page_table.cc')
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Source('translating_port.cc')
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