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gpu-compute: replace uint32_t* casts with bits API calls

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The uint32_t* casting was challenging to fully understand what was
being done at a glance. Replaced with calls to various bits functions
as it's functionally equivalent and much more clear.

This also fixes a segfault in GPUInitAbi DPRINTFs from a mis-typed
uint32_t* cast.

Change-Id: Id5d1863942848dd7a9e5e17e8180c33adbc72f15
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34677
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Kyle Roarty
2020-09-16 16:58:05 -05:00
parent 87328c2fc1
commit 347d7644eb
2 changed files with 16 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/gpu-compute/fetch_unit.cc
View File

@@ -33,6 +33,7 @@
#include "gpu-compute/fetch_unit.hh"
#include "base/bitfield.hh"
#include "debug/GPUFetch.hh"
#include "debug/GPUPort.hh"
#include "debug/GPUTLB.hh"
@@ -576,7 +577,8 @@ FetchUnit::FetchBufDesc::decodeSplitInst()
int num_dwords = sizeof(TheGpuISA::RawMachInst) / dword_size;
for (int i = 0; i < num_dwords; ++i) {
((uint32_t*)(&split_inst))[i] = *reinterpret_cast<uint32_t*>(readPtr);
replaceBits(split_inst, 32*(i+1)-1, 32*i,
*reinterpret_cast<uint32_t*>(readPtr));
if (readPtr + dword_size >= bufEnd) {
readPtr = bufStart;
}

25
src/gpu-compute/wavefront.cc
View File

@@ -33,6 +33,7 @@
#include "gpu-compute/wavefront.hh"
#include "base/bitfield.hh"
#include "debug/GPUExec.hh"
#include "debug/GPUInitAbi.hh"
#include "debug/WavefrontStack.hh"
@@ -257,23 +258,23 @@ Wavefront::initRegState(HSAQueueEntry *task, int wgSizeInWorkItems)
physSgprIdx =
computeUnit->registerManager->mapSgpr(this, regInitIdx);
computeUnit->srf[simdId]->write(physSgprIdx,
((uint32_t*)&host_disp_pkt_addr)[0]);
bits(host_disp_pkt_addr, 31, 0));
++regInitIdx;
DPRINTF(GPUInitAbi, "CU%d: WF[%d][%d]: wave[%d] "
"Setting DispatchPtr: s[%d] = %x\n",
computeUnit->cu_id, simdId,
wfSlotId, wfDynId, physSgprIdx,
((uint32_t*)&host_disp_pkt_addr)[0]);
bits(host_disp_pkt_addr, 31, 0));
physSgprIdx =
computeUnit->registerManager->mapSgpr(this, regInitIdx);
computeUnit->srf[simdId]->write(physSgprIdx,
((uint32_t*)&host_disp_pkt_addr)[1]);
bits(host_disp_pkt_addr, 63, 32));
DPRINTF(GPUInitAbi, "CU%d: WF[%d][%d]: wave[%d] "
"Setting DispatchPtr: s[%d] = %x\n",
computeUnit->cu_id, simdId,
wfSlotId, wfDynId, physSgprIdx,
((uint32_t*)&host_disp_pkt_addr)[1]);
bits(host_disp_pkt_addr, 63, 32));
++regInitIdx;
break;
@@ -281,23 +282,23 @@ Wavefront::initRegState(HSAQueueEntry *task, int wgSizeInWorkItems)
physSgprIdx =
computeUnit->registerManager->mapSgpr(this, regInitIdx);
computeUnit->srf[simdId]->write(physSgprIdx,
((uint32_t*)&task->hostAMDQueueAddr)[0]);
bits(task->hostAMDQueueAddr, 31, 0));
++regInitIdx;
DPRINTF(GPUInitAbi, "CU%d: WF[%d][%d]: wave[%d] "
"Setting QueuePtr: s[%d] = %x\n",
computeUnit->cu_id, simdId,
wfSlotId, wfDynId, physSgprIdx,
((uint32_t*)&task->hostAMDQueueAddr)[0]);
bits(task->hostAMDQueueAddr, 31, 0));
physSgprIdx =
computeUnit->registerManager->mapSgpr(this, regInitIdx);
computeUnit->srf[simdId]->write(physSgprIdx,
((uint32_t*)&task->hostAMDQueueAddr)[1]);
bits(task->hostAMDQueueAddr, 63, 32));
DPRINTF(GPUInitAbi, "CU%d: WF[%d][%d]: wave[%d] "
"Setting QueuePtr: s[%d] = %x\n",
computeUnit->cu_id, simdId,
wfSlotId, wfDynId, physSgprIdx,
((uint32_t*)&task->hostAMDQueueAddr)[1]);
bits(task->hostAMDQueueAddr, 63, 32));
++regInitIdx;
break;
@@ -305,23 +306,23 @@ Wavefront::initRegState(HSAQueueEntry *task, int wgSizeInWorkItems)
physSgprIdx =
computeUnit->registerManager->mapSgpr(this, regInitIdx);
computeUnit->srf[simdId]->write(physSgprIdx,
((uint32_t*)&kernarg_addr)[0]);
bits(kernarg_addr, 31, 0));
++regInitIdx;
DPRINTF(GPUInitAbi, "CU%d: WF[%d][%d]: wave[%d] "
"Setting KernargSegPtr: s[%d] = %x\n",
computeUnit->cu_id, simdId,
wfSlotId, wfDynId, physSgprIdx,
((uint32_t*)kernarg_addr)[0]);
bits(kernarg_addr, 31, 0));
physSgprIdx =
computeUnit->registerManager->mapSgpr(this, regInitIdx);
computeUnit->srf[simdId]->write(physSgprIdx,
((uint32_t*)&kernarg_addr)[1]);
bits(kernarg_addr, 63, 32));
DPRINTF(GPUInitAbi, "CU%d: WF[%d][%d]: wave[%d] "
"Setting KernargSegPtr: s[%d] = %x\n",
computeUnit->cu_id, simdId,
wfSlotId, wfDynId, physSgprIdx,
((uint32_t*)kernarg_addr)[1]);
bits(kernarg_addr, 63, 32));
++regInitIdx;
break;