tests: Removed 20.parser tests
In an effort to cleanup the old tests, and migrate useful tests to be executed via `test/main.py`, it has been decided that the `test/long/se/70.twolf` tests should be removed. Jira: https://gem5.atlassian.net/browse/GEM5-109 Change-Id: Ie0c0cd310ee51a37e80a84af3bf1cb603061da7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24384 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Bobby R. Bruce
@@ -1,997 +0,0 @@
|
||||
[root]
|
||||
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|
||||
children=system
|
||||
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|
||||
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|
||||
sim_quantum=0
|
||||
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|
||||
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|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
kernel=
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
memories=system.physmem
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
[system.clk_domain]
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
[system.cpu]
|
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|
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children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
[system.cpu.branchPred]
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||||
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||||
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||||
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||||
[system.cpu.dcache]
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
[system.cpu.dcache.tags]
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
[system.cpu.dstage2_mmu]
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||||
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||||
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||||
[system.cpu.dstage2_mmu.stage2_tlb]
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||||
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||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
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||||
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||||
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|
||||
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|
||||
|
||||
[system.cpu.dtb]
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
[system.cpu.dtb.walker]
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.executeFuncUnits]
|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
[system.cpu.executeFuncUnits.funcUnits0]
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||||
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||||
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||||
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||||
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||||
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[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
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||||
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||||
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||||
[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
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||||
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||||
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||||
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||||
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[system.cpu.executeFuncUnits.funcUnits1]
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||||
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||||
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||||
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||||
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||||
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[system.cpu.executeFuncUnits.funcUnits1.timings]
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||||
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[system.cpu.executeFuncUnits.funcUnits2]
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||||
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[system.cpu.executeFuncUnits.funcUnits2.opClasses]
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||||
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||||
[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
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[system.cpu.executeFuncUnits.funcUnits2.timings]
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||||
[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
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||||
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||||
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||||
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||||
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||||
[system.cpu.executeFuncUnits.funcUnits3]
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||||
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||||
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||||
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|
||||
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||||
issueLat=9
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||||
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
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||||
opLat=9
|
||||
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|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits3.opClasses]
|
||||
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|
||||
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|
||||
eventq_index=0
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||||
opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
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|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4]
|
||||
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|
||||
children=opClasses timings
|
||||
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|
||||
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|
||||
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||||
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|
||||
opLat=6
|
||||
timings=system.cpu.executeFuncUnits.funcUnits4.timings
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses]
|
||||
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|
||||
children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
|
||||
eventq_index=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=FloatAdd
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=FloatCmp
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=FloatCvt
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=FloatMult
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=FloatDiv
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
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|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdAdd
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdAddAcc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdAlu
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdCmp
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdCvt
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdMisc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdMult
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdMultAcc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdShift
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdShiftAcc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdSqrt
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatAdd
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatAlu
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatCmp
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatCvt
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatDiv
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMisc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMult
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMultAcc
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=SimdFloatSqrt
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.timings]
|
||||
type=MinorFUTiming
|
||||
children=opClasses
|
||||
description=FloatSimd
|
||||
eventq_index=0
|
||||
extraAssumedLat=0
|
||||
extraCommitLat=0
|
||||
extraCommitLatExpr=Null
|
||||
mask=0
|
||||
match=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses
|
||||
srcRegsRelativeLats=2
|
||||
suppress=false
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses]
|
||||
type=MinorOpClassSet
|
||||
eventq_index=0
|
||||
opClasses=
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5]
|
||||
type=MinorFU
|
||||
children=opClasses timings
|
||||
cantForwardFromFUIndices=
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses
|
||||
opLat=1
|
||||
timings=system.cpu.executeFuncUnits.funcUnits5.timings
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5.opClasses]
|
||||
type=MinorOpClassSet
|
||||
children=opClasses0 opClasses1
|
||||
eventq_index=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=MemRead
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=MemWrite
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5.timings]
|
||||
type=MinorFUTiming
|
||||
children=opClasses
|
||||
description=Mem
|
||||
eventq_index=0
|
||||
extraAssumedLat=2
|
||||
extraCommitLat=0
|
||||
extraCommitLatExpr=Null
|
||||
mask=0
|
||||
match=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses
|
||||
srcRegsRelativeLats=1
|
||||
suppress=false
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses]
|
||||
type=MinorOpClassSet
|
||||
eventq_index=0
|
||||
opClasses=
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits6]
|
||||
type=MinorFU
|
||||
children=opClasses
|
||||
cantForwardFromFUIndices=
|
||||
eventq_index=0
|
||||
issueLat=1
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses
|
||||
opLat=1
|
||||
timings=
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits6.opClasses]
|
||||
type=MinorOpClassSet
|
||||
children=opClasses0 opClasses1
|
||||
eventq_index=0
|
||||
opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=IprAccess
|
||||
|
||||
[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1]
|
||||
type=MinorOpClass
|
||||
eventq_index=0
|
||||
opClass=InstPrefetch
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=131072
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_aa64pfr0_el1=34
|
||||
id_aa64pfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
id_pfr0=49
|
||||
id_pfr1=4113
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.toL2Bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
|
||||
kvmInSE=false
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
|
||||
@@ -1,73 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 11 2016 00:00:58
|
||||
gem5 started Oct 13 2016 20:47:38
|
||||
gem5 executing on e108600-lin, pid 17428
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/minor-timing
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
Reading the dictionary files: *************************************************
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
info: Increasing stack size by one page.
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
info: Increasing stack size by one page.
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 368600034500 because target called exit()
|
||||
@@ -1,948 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.368651 # Number of seconds simulated
|
||||
sim_ticks 368651185500 # Number of ticks simulated
|
||||
final_tick 368651185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 378825 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 410318 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 275680946 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 276920 # Number of bytes of host memory used
|
||||
host_seconds 1337.24 # Real time elapsed on the host
|
||||
sim_insts 506579366 # Number of instructions simulated
|
||||
sim_ops 548692589 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 179712 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 9049216 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 9228928 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 179712 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 179712 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6241472 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6241472 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2808 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 141394 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 144202 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 97523 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 97523 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 487485 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 24546825 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 25034310 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 487485 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 487485 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 16930563 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 16930563 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 16930563 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 487485 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 24546825 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41964873 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 144202 # Number of read requests accepted
|
||||
system.physmem.writeReqs 97523 # Number of write requests accepted
|
||||
system.physmem.readBursts 144202 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 97523 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 9222208 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 6240000 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 9228928 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 6241472 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 9327 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 8931 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 8953 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 8672 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 9421 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 9371 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 8975 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 8126 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 8631 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 8699 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 8760 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 9484 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 9351 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 9541 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 8731 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 9124 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 6232 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 6121 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 6045 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 5902 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 6267 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 6264 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 6070 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 5535 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 5819 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 5921 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 5985 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 6509 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 6365 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 6345 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 6018 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 6102 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 368651160000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 144202 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 97523 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 143745 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 333 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 2715 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 2868 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 5695 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 5740 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 5743 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 5747 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 5746 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 5744 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 5743 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 5746 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 5753 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 5752 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 5766 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 5758 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 5756 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 64014 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 241.533165 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 161.867212 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 241.438904 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 22835 35.67% 35.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 18294 28.58% 64.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 7516 11.74% 75.99% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 7993 12.49% 88.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2085 3.26% 91.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1176 1.84% 93.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 786 1.23% 94.80% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 642 1.00% 95.80% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 2687 4.20% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 64014 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 5742 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 25.094566 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 375.615355 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 5739 99.95% 99.95% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 5742 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 5742 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.980146 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.950575 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 1.005103 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 2875 50.07% 50.07% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 152 2.65% 52.72% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 2688 46.81% 99.53% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 17 0.30% 99.83% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 6 0.10% 99.93% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 2 0.03% 99.97% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 5742 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 3587327500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 6289146250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 720485000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 24895.23 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 43645.23 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 25.02 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 25.03 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 16.93 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.33 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 19.95 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 110436 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 67138 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 76.64 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1525084.95 # Average gap between requests
|
||||
system.physmem.pageHitRate 73.49 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 229772340 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 122107920 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 512480640 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 252835920 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 7717419840.000002 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 4012679730 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 354856800 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.actPowerDownEnergy 24782953050 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_0.prePowerDownEnergy 8303052480 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_0.selfRefreshEnergy 68829850950 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_0.totalEnergy 115120015110 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 312.273551 # Core power per rank (mW)
|
||||
system.physmem_0.totalIdleTime 358922434750 # Total Idle time Per DRAM Rank
|
||||
system.physmem_0.memoryStateTime::IDLE 536706250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 3274898000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::SREF 282951785250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 21622731000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 5916696250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 54348368750 # Time in different power states
|
||||
system.physmem_1.actEnergy 227351880 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 120825210 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 516371940 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 256114080 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 7627682400.000002 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 3951722790 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 344311680 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.actPowerDownEnergy 24510614460 # Energy for active power-down per rank (pJ)
|
||||
system.physmem_1.prePowerDownEnergy 8148381600 # Energy for precharge power-down per rank (pJ)
|
||||
system.physmem_1.selfRefreshEnergy 69110361900 # Energy for self refresh per rank (pJ)
|
||||
system.physmem_1.totalEnergy 114816583080 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 311.450463 # Core power per rank (mW)
|
||||
system.physmem_1.totalIdleTime 359082796500 # Total Idle time Per DRAM Rank
|
||||
system.physmem_1.memoryStateTime::IDLE 515499000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 3236866000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::SREF 284111116500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 21219892250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 5815970250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 53751841500 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 132096754 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 98183062 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5916233 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 68556674 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 60606255 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 88.403144 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 10020256 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 19127 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 3891736 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 3883139 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 8597 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 54132 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
||||
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||||
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||||
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||||
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.numSyscalls 548 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 737302371 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 506579366 # Number of instructions committed
|
||||
system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 12932918 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.455453 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.687071 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
|
||||
system.cpu.op_class_0::MemWrite 56860206 10.36% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 548692589 # Class of committed instruction
|
||||
system.cpu.tickCycles 694166450 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 43135921 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 1141334 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4070.216677 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 171085721 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1145430 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 149.363751 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 5072789500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.216677 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 548 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3502 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 346341652 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 346341652 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114567880 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 114567880 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53537967 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 53537967 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 2792 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 2792 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168105847 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168105847 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168108639 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168108639 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 811293 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 811293 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 701082 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 701082 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1512375 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1512375 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1512390 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1512390 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14512864500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 14512864500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24025186500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 24025186500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 38538051000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 38538051000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 38538051000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 38538051000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 115379173 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 115379173 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2807 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 2807 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 169618222 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 169618222 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 169621029 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 169621029 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005344 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.005344 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.008916 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.008916 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.008916 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.008916 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17888.561223 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17888.561223 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34268.725342 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34268.725342 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25481.809075 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 25481.809075 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25481.556345 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 25481.556345 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 1068964 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1068964 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22242 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 22242 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344715 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 344715 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 366957 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 366957 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 366957 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 366957 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789051 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 789051 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356367 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 356367 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1145418 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1145418 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1145430 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1145430 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13418418500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 13418418500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12201205500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12201205500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4179500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4179500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25619624000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 25619624000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25623803500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 25623803500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006570 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006570 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004275 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004275 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17005.768322 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17005.768322 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34237.753496 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34237.753496 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 348291.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 348291.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22367.052028 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22367.052028 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22370.466550 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22370.466550 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 18132 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1186.493230 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 199187334 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 20004 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 9957.375225 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1186.493230 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.579342 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.579342 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 318 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1398 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 398434680 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 398434680 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 199187334 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 199187334 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 199187334 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 199187334 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 199187334 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 199187334 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 20004 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 20004 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 20004 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 20004 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 20004 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 20004 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 543340500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 543340500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 543340500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 543340500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 543340500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 543340500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 199207338 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 199207338 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 199207338 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 199207338 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 199207338 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 199207338 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000100 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000100 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000100 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000100 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000100 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000100 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27161.592681 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27161.592681 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27161.592681 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27161.592681 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27161.592681 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27161.592681 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 18132 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 18132 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20004 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 20004 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 20004 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 20004 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 20004 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 20004 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 523336500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 523336500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 523336500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 523336500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 523336500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 523336500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000100 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000100 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000100 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26161.592681 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26161.592681 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26161.592681 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 26161.592681 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26161.592681 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 26161.592681 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 112700 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29077.009680 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2174426 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 145468 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 14.947796 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 102124248000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 135.271970 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.139631 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28633.598078 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.004128 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009404 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.873828 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.887360 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 988 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31579 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 18704732 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 18704732 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1068964 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1068964 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 17895 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 17895 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 255662 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 255662 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17195 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 17195 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748361 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 748361 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 17195 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1004023 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1021218 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 17195 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1004023 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1021218 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 100957 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 100957 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2809 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2809 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40450 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 40450 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2809 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 141407 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 144216 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2809 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 141407 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 144216 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8984700500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 8984700500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312111000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 312111000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4361406500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4361406500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 312111000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 13346107000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 13658218000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 312111000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 13346107000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 13658218000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068964 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1068964 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 17895 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 17895 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356619 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 356619 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20004 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 20004 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788811 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 788811 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 20004 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1145430 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1165434 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 20004 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1145430 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1165434 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283095 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.283095 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140422 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140422 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051280 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051280 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140422 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.123453 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.123744 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140422 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.123453 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.123744 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88995.319790 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88995.319790 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111111.071556 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111111.071556 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107822.163164 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107822.163164 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111111.071556 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94380.808588 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 94706.676097 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111111.071556 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94380.808588 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 94706.676097 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 97523 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 97523 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100957 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 100957 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2808 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2808 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40437 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40437 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 141394 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 144202 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2808 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 141394 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 144202 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7975130500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7975130500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 283956000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 283956000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3955182000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3955182000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283956000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11930312500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 12214268500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283956000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11930312500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 12214268500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283095 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283095 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140372 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051263 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051263 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123442 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123732 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123442 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123732 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78995.319790 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78995.319790 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101123.931624 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101123.931624 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97810.965205 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97810.965205 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101123.931624 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84376.370284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84702.490257 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101123.931624 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84376.370284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84702.490257 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 2324900 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159536 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4992 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 808815 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1166487 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 18132 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 87547 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 356619 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 356619 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 20004 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 788811 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58140 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432194 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3490334 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440704 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141721216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 144161920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 112700 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 6241472 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1278134 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.006011 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.077328 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1270454 99.40% 99.40% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 7677 0.60% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1278134 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2249546000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 30029453 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1718153483 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.snoop_filter.tot_requests 254284 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 110251 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 43245 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 97523 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 12559 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 100957 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 100957 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 43245 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398486 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 398486 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15470400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 15470400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 144202 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 144202 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 144202 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 684899000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 765515250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,962 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=16
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=0
|
||||
SQEntries=16
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
branchPred=system.cpu.branchPred
|
||||
cacheStorePorts=200
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=16
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=3
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=3
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=false
|
||||
numIQEntries=32
|
||||
numPhysCCRegs=640
|
||||
numPhysFloatRegs=192
|
||||
numPhysIntRegs=128
|
||||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=1
|
||||
renameToROBDelay=1
|
||||
renameWidth=3
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.branchPred]
|
||||
type=BiModeBP
|
||||
BTBEntries=2048
|
||||
BTBTagSize=18
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=6
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=8
|
||||
write_buffers=16
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IntDiv
|
||||
opLat=12
|
||||
pipelined=false
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=MemRead
|
||||
opLat=2
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMemRead
|
||||
opLat=2
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=MemWrite
|
||||
opLat=2
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMemWrite
|
||||
opLat=2
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdAdd
|
||||
opLat=4
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdAddAcc
|
||||
opLat=4
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdAlu
|
||||
opLat=4
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdCmp
|
||||
opLat=4
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdCvt
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdMisc
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdMult
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdMultAcc
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdShift
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdShiftAcc
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdSqrt
|
||||
opLat=9
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatAdd
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatAlu
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatCmp
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatCvt
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatDiv
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMisc
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMult
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=9
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList20]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatAdd
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList21]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatCmp
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList22]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatCvt
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList23]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatDiv
|
||||
opLat=9
|
||||
pipelined=false
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList24]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatSqrt
|
||||
opLat=33
|
||||
pipelined=false
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList25]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList26]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMultAcc
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList27]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMisc
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=1
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=1
|
||||
sequential_access=false
|
||||
size=32768
|
||||
system=system
|
||||
tag_latency=1
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=8
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=1
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
tag_latency=1
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=Cache
|
||||
children=prefetcher tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_excl
|
||||
data_latency=12
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=true
|
||||
prefetcher=system.cpu.l2cache.prefetcher
|
||||
response_latency=12
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
system=system
|
||||
tag_latency=12
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=8
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.prefetcher]
|
||||
type=StridePrefetcher
|
||||
cache_snoop=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
degree=8
|
||||
eventq_index=0
|
||||
latency=1
|
||||
max_conf=7
|
||||
min_conf=0
|
||||
on_data=true
|
||||
on_inst=true
|
||||
on_miss=false
|
||||
on_read=true
|
||||
on_write=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
queue_filter=true
|
||||
queue_size=32
|
||||
queue_squash=true
|
||||
start_conf=4
|
||||
sys=system
|
||||
table_assoc=4
|
||||
table_sets=16
|
||||
tag_prefetch=true
|
||||
thresh_conf=4
|
||||
use_master_id=true
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=RandomRepl
|
||||
assoc=16
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=12
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1048576
|
||||
tag_latency=12
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.toL2Bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -1,7 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
@@ -1,70 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 17:55:48
|
||||
gem5 started Apr 3 2017 18:14:44
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 57363
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
||||
Reading the dictionary files: *************************************************
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 235850129000 because exiting with last active thread context
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,330 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -1,5 +0,0 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
@@ -1,70 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 17:55:48
|
||||
gem5 started Apr 3 2017 17:56:13
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54223
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-atomic
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
||||
Reading the dictionary files: *************************************************
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 279360903000 because exiting with last active thread context
|
||||
@@ -1,262 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.279361
|
||||
sim_ticks 279360903000
|
||||
final_tick 279360903000
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 937755
|
||||
host_op_rate 1015713
|
||||
host_tick_rate 517139598
|
||||
host_mem_usage 274756
|
||||
host_seconds 540.20
|
||||
sim_insts 506578818
|
||||
sim_ops 548692039
|
||||
system.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000
|
||||
system.physmem.bytes_read::cpu.inst 2066434344
|
||||
system.physmem.bytes_read::cpu.data 422848347
|
||||
system.physmem.bytes_read::total 2489282691
|
||||
system.physmem.bytes_inst_read::cpu.inst 2066434344
|
||||
system.physmem.bytes_inst_read::total 2066434344
|
||||
system.physmem.bytes_written::cpu.data 216066596
|
||||
system.physmem.bytes_written::total 216066596
|
||||
system.physmem.num_reads::cpu.inst 516608586
|
||||
system.physmem.num_reads::cpu.data 115590054
|
||||
system.physmem.num_reads::total 632198640
|
||||
system.physmem.num_writes::cpu.data 55727590
|
||||
system.physmem.num_writes::total 55727590
|
||||
system.physmem.bw_read::cpu.inst 7397006245
|
||||
system.physmem.bw_read::cpu.data 1513627506
|
||||
system.physmem.bw_read::total 8910633751
|
||||
system.physmem.bw_inst_read::cpu.inst 7397006245
|
||||
system.physmem.bw_inst_read::total 7397006245
|
||||
system.physmem.bw_write::cpu.data 773431764
|
||||
system.physmem.bw_write::total 773431764
|
||||
system.physmem.bw_total::cpu.inst 7397006245
|
||||
system.physmem.bw_total::cpu.data 2287059270
|
||||
system.physmem.bw_total::total 9684065515
|
||||
system.pwrStateResidencyTicks::UNDEFINED 279360903000
|
||||
system.cpu_clk_domain.clock 500
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
|
||||
system.cpu.dtb.walker.walks 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dtb.inst_hits 0
|
||||
system.cpu.dtb.inst_misses 0
|
||||
system.cpu.dtb.read_hits 0
|
||||
system.cpu.dtb.read_misses 0
|
||||
system.cpu.dtb.write_hits 0
|
||||
system.cpu.dtb.write_misses 0
|
||||
system.cpu.dtb.flush_tlb 0
|
||||
system.cpu.dtb.flush_tlb_mva 0
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0
|
||||
system.cpu.dtb.flush_tlb_asid 0
|
||||
system.cpu.dtb.flush_entries 0
|
||||
system.cpu.dtb.align_faults 0
|
||||
system.cpu.dtb.prefetch_faults 0
|
||||
system.cpu.dtb.domain_faults 0
|
||||
system.cpu.dtb.perms_faults 0
|
||||
system.cpu.dtb.read_accesses 0
|
||||
system.cpu.dtb.write_accesses 0
|
||||
system.cpu.dtb.inst_accesses 0
|
||||
system.cpu.dtb.hits 0
|
||||
system.cpu.dtb.misses 0
|
||||
system.cpu.dtb.accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
|
||||
system.cpu.itb.walker.walks 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.itb.inst_hits 0
|
||||
system.cpu.itb.inst_misses 0
|
||||
system.cpu.itb.read_hits 0
|
||||
system.cpu.itb.read_misses 0
|
||||
system.cpu.itb.write_hits 0
|
||||
system.cpu.itb.write_misses 0
|
||||
system.cpu.itb.flush_tlb 0
|
||||
system.cpu.itb.flush_tlb_mva 0
|
||||
system.cpu.itb.flush_tlb_mva_asid 0
|
||||
system.cpu.itb.flush_tlb_asid 0
|
||||
system.cpu.itb.flush_entries 0
|
||||
system.cpu.itb.align_faults 0
|
||||
system.cpu.itb.prefetch_faults 0
|
||||
system.cpu.itb.domain_faults 0
|
||||
system.cpu.itb.perms_faults 0
|
||||
system.cpu.itb.read_accesses 0
|
||||
system.cpu.itb.write_accesses 0
|
||||
system.cpu.itb.inst_accesses 0
|
||||
system.cpu.itb.hits 0
|
||||
system.cpu.itb.misses 0
|
||||
system.cpu.itb.accesses 0
|
||||
system.cpu.workload.numSyscalls 548
|
||||
system.cpu.pwrStateResidencyTicks::ON 279360903000
|
||||
system.cpu.numCycles 558721807
|
||||
system.cpu.numWorkItemsStarted 0
|
||||
system.cpu.numWorkItemsCompleted 0
|
||||
system.cpu.committedInsts 506578818
|
||||
system.cpu.committedOps 548692039
|
||||
system.cpu.num_int_alu_accesses 448447005
|
||||
system.cpu.num_fp_alu_accesses 16
|
||||
system.cpu.num_func_calls 19311615
|
||||
system.cpu.num_conditional_control_insts 90670594
|
||||
system.cpu.num_int_insts 448447005
|
||||
system.cpu.num_fp_insts 16
|
||||
system.cpu.num_int_register_reads 749023721
|
||||
system.cpu.num_int_register_writes 289993515
|
||||
system.cpu.num_fp_register_reads 16
|
||||
system.cpu.num_fp_register_writes 0
|
||||
system.cpu.num_cc_register_reads 1634221880
|
||||
system.cpu.num_cc_register_writes 344062197
|
||||
system.cpu.num_mem_refs 172743505
|
||||
system.cpu.num_load_insts 115883283
|
||||
system.cpu.num_store_insts 56860222
|
||||
system.cpu.num_idle_cycles 0
|
||||
system.cpu.num_busy_cycles 558721807
|
||||
system.cpu.not_idle_fraction 1
|
||||
system.cpu.idle_fraction 0
|
||||
system.cpu.Branches 121552863
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00%
|
||||
system.cpu.op_class::IntAlu 375609862 68.46% 68.46%
|
||||
system.cpu.op_class::IntMult 339219 0.06% 68.52%
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.52%
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.52%
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 68.52%
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 68.52%
|
||||
system.cpu.op_class::FloatMult 0 0.00% 68.52%
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 68.52%
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 68.52%
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 68.52%
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdMult 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdShift 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52%
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52%
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52%
|
||||
system.cpu.op_class::MemRead 115883283 21.12% 89.64%
|
||||
system.cpu.op_class::MemWrite 56860206 10.36% 100.00%
|
||||
system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
|
||||
system.cpu.op_class::FloatMemWrite 16 0.00% 100.00%
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00%
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
|
||||
system.cpu.op_class::total 548692589
|
||||
system.membus.snoop_filter.tot_requests 0
|
||||
system.membus.snoop_filter.hit_single_requests 0
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000
|
||||
system.membus.trans_dist::ReadReq 630707528
|
||||
system.membus.trans_dist::ReadResp 632196069
|
||||
system.membus.trans_dist::WriteReq 54239049
|
||||
system.membus.trans_dist::WriteResp 54239049
|
||||
system.membus.trans_dist::SoftPFReq 2571
|
||||
system.membus.trans_dist::SoftPFResp 2571
|
||||
system.membus.trans_dist::LoadLockedReq 1488541
|
||||
system.membus.trans_dist::StoreCondReq 1488541
|
||||
system.membus.trans_dist::StoreCondResp 1488541
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288
|
||||
system.membus.pkt_count::total 1375852460
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943
|
||||
system.membus.pkt_size::total 2705349287
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 687926230
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 687926230 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 687926230
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,499 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dstage2_mmu=system.cpu.dstage2_mmu
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
istage2_mmu=system.cpu.istage2_mmu
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=262144
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.dstage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.dtb
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=131072
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=ArmInterrupts
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.isa]
|
||||
type=ArmISA
|
||||
decoderFlavour=Generic
|
||||
eventq_index=0
|
||||
fpsid=1090793632
|
||||
id_aa64afr0_el1=0
|
||||
id_aa64afr1_el1=0
|
||||
id_aa64dfr0_el1=1052678
|
||||
id_aa64dfr1_el1=0
|
||||
id_aa64isar0_el1=0
|
||||
id_aa64isar1_el1=0
|
||||
id_aa64mmfr0_el1=15728642
|
||||
id_aa64mmfr1_el1=0
|
||||
id_isar0=34607377
|
||||
id_isar1=34677009
|
||||
id_isar2=555950401
|
||||
id_isar3=17899825
|
||||
id_isar4=268501314
|
||||
id_isar5=0
|
||||
id_mmfr0=270536963
|
||||
id_mmfr1=0
|
||||
id_mmfr2=19070976
|
||||
id_mmfr3=34611729
|
||||
midr=1091551472
|
||||
pmu=Null
|
||||
system=system
|
||||
|
||||
[system.cpu.istage2_mmu]
|
||||
type=ArmStage2MMU
|
||||
children=stage2_tlb
|
||||
eventq_index=0
|
||||
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
|
||||
sys=system
|
||||
tlb=system.cpu.itb
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
size=32
|
||||
walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
||||
|
||||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=ArmTLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
tag_latency=20
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.toL2Bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser
|
||||
gid=100
|
||||
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port
|
||||
slave=system.system_port system.cpu.l2cache.mem_side
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -1,5 +0,0 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
@@ -1,70 +0,0 @@
|
||||
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 17:55:48
|
||||
gem5 started Apr 3 2017 18:35:18
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 61430
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-timing
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
||||
Reading the dictionary files: *************************************************
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 708700329500 because exiting with last active thread context
|
||||
@@ -1,685 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.708700
|
||||
sim_ticks 708700329500
|
||||
final_tick 708700329500
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 679420
|
||||
host_op_rate 735782
|
||||
host_tick_rate 953505845
|
||||
host_mem_usage 285772
|
||||
host_seconds 743.26
|
||||
sim_insts 504984064
|
||||
sim_ops 546875315
|
||||
system.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500
|
||||
system.physmem.bytes_read::cpu.inst 147392
|
||||
system.physmem.bytes_read::cpu.data 8988096
|
||||
system.physmem.bytes_read::total 9135488
|
||||
system.physmem.bytes_inst_read::cpu.inst 147392
|
||||
system.physmem.bytes_inst_read::total 147392
|
||||
system.physmem.bytes_written::writebacks 6185472
|
||||
system.physmem.bytes_written::total 6185472
|
||||
system.physmem.num_reads::cpu.inst 2303
|
||||
system.physmem.num_reads::cpu.data 140439
|
||||
system.physmem.num_reads::total 142742
|
||||
system.physmem.num_writes::writebacks 96648
|
||||
system.physmem.num_writes::total 96648
|
||||
system.physmem.bw_read::cpu.inst 207975
|
||||
system.physmem.bw_read::cpu.data 12682506
|
||||
system.physmem.bw_read::total 12890481
|
||||
system.physmem.bw_inst_read::cpu.inst 207975
|
||||
system.physmem.bw_inst_read::total 207975
|
||||
system.physmem.bw_write::writebacks 8727909
|
||||
system.physmem.bw_write::total 8727909
|
||||
system.physmem.bw_total::writebacks 8727909
|
||||
system.physmem.bw_total::cpu.inst 207975
|
||||
system.physmem.bw_total::cpu.data 12682506
|
||||
system.physmem.bw_total::total 21618390
|
||||
system.pwrStateResidencyTicks::UNDEFINED 708700329500
|
||||
system.cpu_clk_domain.clock 500
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500
|
||||
system.cpu.dtb.walker.walks 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.dtb.inst_hits 0
|
||||
system.cpu.dtb.inst_misses 0
|
||||
system.cpu.dtb.read_hits 0
|
||||
system.cpu.dtb.read_misses 0
|
||||
system.cpu.dtb.write_hits 0
|
||||
system.cpu.dtb.write_misses 0
|
||||
system.cpu.dtb.flush_tlb 0
|
||||
system.cpu.dtb.flush_tlb_mva 0
|
||||
system.cpu.dtb.flush_tlb_mva_asid 0
|
||||
system.cpu.dtb.flush_tlb_asid 0
|
||||
system.cpu.dtb.flush_entries 0
|
||||
system.cpu.dtb.align_faults 0
|
||||
system.cpu.dtb.prefetch_faults 0
|
||||
system.cpu.dtb.domain_faults 0
|
||||
system.cpu.dtb.perms_faults 0
|
||||
system.cpu.dtb.read_accesses 0
|
||||
system.cpu.dtb.write_accesses 0
|
||||
system.cpu.dtb.inst_accesses 0
|
||||
system.cpu.dtb.hits 0
|
||||
system.cpu.dtb.misses 0
|
||||
system.cpu.dtb.accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.align_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500
|
||||
system.cpu.itb.walker.walks 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 0
|
||||
system.cpu.itb.inst_hits 0
|
||||
system.cpu.itb.inst_misses 0
|
||||
system.cpu.itb.read_hits 0
|
||||
system.cpu.itb.read_misses 0
|
||||
system.cpu.itb.write_hits 0
|
||||
system.cpu.itb.write_misses 0
|
||||
system.cpu.itb.flush_tlb 0
|
||||
system.cpu.itb.flush_tlb_mva 0
|
||||
system.cpu.itb.flush_tlb_mva_asid 0
|
||||
system.cpu.itb.flush_tlb_asid 0
|
||||
system.cpu.itb.flush_entries 0
|
||||
system.cpu.itb.align_faults 0
|
||||
system.cpu.itb.prefetch_faults 0
|
||||
system.cpu.itb.domain_faults 0
|
||||
system.cpu.itb.perms_faults 0
|
||||
system.cpu.itb.read_accesses 0
|
||||
system.cpu.itb.write_accesses 0
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500
|
||||
system.cpu.l2cache.tags.replacements 110813
|
||||
system.cpu.l2cache.tags.tagsinuse 28700.010798
|
||||
system.cpu.l2cache.tags.total_refs 2150809
|
||||
system.cpu.l2cache.tags.sampled_refs 143581
|
||||
system.cpu.l2cache.tags.avg_refs 14.979761
|
||||
system.cpu.l2cache.tags.warmup_cycle 210357436000
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 80.467975
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 239.840136
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28379.702687
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.002456
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007319
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.866080
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.875855
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 661
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 1
|
||||
system.cpu.l2cache.tags.tag_accesses 18498717
|
||||
system.cpu.l2cache.tags.data_accesses 18498717
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708700329500
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1065429
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1065429
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 9751
|
||||
system.cpu.l2cache.WritebackClean_hits::total 9751
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 255675
|
||||
system.cpu.l2cache.ReadExReq_hits::total 255675
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 9218
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744258
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 744258
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 9218
|
||||
system.cpu.l2cache.demand_hits::cpu.data 999933
|
||||
system.cpu.l2cache.demand_hits::total 1009151
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 9218
|
||||
system.cpu.l2cache.overall_hits::cpu.data 999933
|
||||
system.cpu.l2cache.overall_hits::total 1009151
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 100833
|
||||
system.cpu.l2cache.ReadExReq_misses::total 100833
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2303
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39606
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 39606
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2303
|
||||
system.cpu.l2cache.demand_misses::cpu.data 140439
|
||||
system.cpu.l2cache.demand_misses::total 142742
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2303
|
||||
system.cpu.l2cache.overall_misses::cpu.data 140439
|
||||
system.cpu.l2cache.overall_misses::total 142742
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6104447000
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6104447000
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 139534000
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 139534000
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2398500500
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2398500500
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 139534000
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8502947500
|
||||
system.cpu.l2cache.demand_miss_latency::total 8642481500
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 139534000
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8502947500
|
||||
system.cpu.l2cache.overall_miss_latency::total 8642481500
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065429
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1065429
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 9751
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 9751
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 356508
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 11521
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 783864
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 11521
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1140372
|
||||
system.cpu.l2cache.demand_accesses::total 1151893
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 11521
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1140372
|
||||
system.cpu.l2cache.overall_accesses::total 1151893
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282835
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.282835
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050527
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050527
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.123152
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.123919
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.123152
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.123919
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60540.170381
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60540.170381
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60587.928789
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60559.018836
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60559.018836
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60587.928789
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60545.485941
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60546.170714
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60587.928789
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60545.485941
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60546.170714
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0
|
||||
system.cpu.l2cache.blocked::no_mshrs 0
|
||||
system.cpu.l2cache.blocked::no_targets 0
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.l2cache.writebacks::writebacks 96648
|
||||
system.cpu.l2cache.writebacks::total 96648
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 2
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100833
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 100833
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39606
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39606
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 140439
|
||||
system.cpu.l2cache.demand_mshr_misses::total 142742
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 140439
|
||||
system.cpu.l2cache.overall_mshr_misses::total 142742
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5096117000
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5096117000
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116504000
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116504000
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2002440500
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2002440500
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116504000
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116504000
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 2297957
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2153
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 795385
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 9788
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 85012
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 356508
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 356508
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020
|
||||
system.cpu.toL2Bus.pkt_count::total 3449850
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264
|
||||
system.cpu.toL2Bus.pkt_size::total 142535040
|
||||
system.cpu.toL2Bus.snoops 110813
|
||||
system.cpu.toL2Bus.snoopTraffic 6185472
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1262706
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004570
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.067461
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54%
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00%
|
||||
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00%
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1262706
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2224195500
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 17281500
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1710558000
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2
|
||||
system.membus.snoop_filter.tot_requests 251405
|
||||
system.membus.snoop_filter.hit_single_requests 108784
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500
|
||||
system.membus.trans_dist::ReadResp 41909
|
||||
system.membus.trans_dist::WritebackDirty 96648
|
||||
system.membus.trans_dist::CleanEvict 12014
|
||||
system.membus.trans_dist::ReadExReq 100833
|
||||
system.membus.trans_dist::ReadExResp 100833
|
||||
system.membus.trans_dist::ReadSharedReq 41909
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146
|
||||
system.membus.pkt_count::total 394146
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960
|
||||
system.membus.pkt_size::total 15320960
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 142743
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 142743 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 142743
|
||||
system.membus.reqLayer0.occupancy 644372828
|
||||
system.membus.reqLayer0.utilization 0.1
|
||||
system.membus.respLayer1.occupancy 713710000
|
||||
system.membus.respLayer1.utilization 0.1
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,924 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kvm_vm=Null
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
LSQCheckLoads=true
|
||||
LSQDepCheckShift=4
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
branchPred=system.cpu.branchPred
|
||||
cacheStorePorts=200
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
cpu_id=0
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fetchBufferSize=64
|
||||
fetchQueueSize=32
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
needsTSO=true
|
||||
numIQEntries=64
|
||||
numPhysCCRegs=1280
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
simpoint_start_insts=
|
||||
smtCommitPolicy=RoundRobin
|
||||
smtFetchPolicy=SingleThread
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtNumFetchingThreads=1
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
socket_id=0
|
||||
squashWidth=8
|
||||
store_set_clear_period=250000
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
trapLatency=13
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.branchPred]
|
||||
type=TournamentBP
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=262144
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=6
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList0.opList
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IntDiv
|
||||
opLat=1
|
||||
pipelined=false
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2 opList3 opList4
|
||||
count=2
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMultAcc
|
||||
opLat=5
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMisc
|
||||
opLat=3
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList3]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
pipelined=false
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList4]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
pipelined=false
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMemRead
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList00]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdAdd
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList01]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdAddAcc
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList02]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdAlu
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList03]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdCmp
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList04]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdCvt
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList05]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdMisc
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList06]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdMult
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList07]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdMultAcc
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList08]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdShift
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList09]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdShiftAcc
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList10]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdSqrt
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList11]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatAdd
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList12]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatAlu
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList13]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatCmp
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList14]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatCvt
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList15]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatDiv
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList16]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMisc
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList17]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMult
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList18]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatMultAcc
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList19]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=SimdFloatSqrt
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=0
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMemWrite
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2 opList3
|
||||
count=4
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList1]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList2]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMemRead
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList3]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=FloatMemWrite
|
||||
opLat=1
|
||||
pipelined=true
|
||||
|
||||
[system.cpu.fuPool.FUList8]
|
||||
type=FUDesc
|
||||
children=opList
|
||||
count=1
|
||||
eventq_index=0
|
||||
opList=system.cpu.fuPool.FUList8.opList
|
||||
|
||||
[system.cpu.fuPool.FUList8.opList]
|
||||
type=OpDesc
|
||||
eventq_index=0
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
pipelined=false
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=131072
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
tag_latency=20
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.toL2Bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.055000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.032000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.032000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.038000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.038000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.157000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.125000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.235000
|
||||
IDD52=0.000000
|
||||
IDD6=0.020000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaCoCh
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10000
|
||||
static_frontend_latency=10000
|
||||
tBURST=5000
|
||||
tCCD_L=0
|
||||
tCK=1250
|
||||
tCL=13750
|
||||
tCS=2500
|
||||
tRAS=35000
|
||||
tRCD=13750
|
||||
tREFI=7800000
|
||||
tRFC=260000
|
||||
tRP=13750
|
||||
tRRD=6000
|
||||
tRRD_L=0
|
||||
tRTP=7500
|
||||
tRTW=2500
|
||||
tWR=15000
|
||||
tWTR=7500
|
||||
tXAW=30000
|
||||
tXP=6000
|
||||
tXPDLL=0
|
||||
tXS=270000
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -1,18 +0,0 @@
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
@@ -1,71 +0,0 @@
|
||||
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 19:05:53
|
||||
gem5 started Apr 3 2017 19:06:22
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87198
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
||||
Reading the dictionary files: *************************************************
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 487050729500 because exiting with last active thread context
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,263 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kvm_vm=Null
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=atomic
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=apic_clk_domain dtb interrupts isa itb tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
fastmem=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.slave[2]
|
||||
icache_port=system.membus.slave[1]
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
system=system
|
||||
port=system.membus.slave[4]
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
int_master=system.membus.slave[5]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
system=system
|
||||
port=system.membus.slave[3]
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -1,6 +0,0 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
@@ -1,71 +0,0 @@
|
||||
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 19:05:53
|
||||
gem5 started Apr 3 2017 19:06:22
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87200
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-atomic
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
||||
Reading the dictionary files: *************************************************
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 885772926000 because exiting with last active thread context
|
||||
@@ -1,145 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.885773
|
||||
sim_ticks 885772926000
|
||||
final_tick 885772926000
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 728826
|
||||
host_op_rate 1348694
|
||||
host_tick_rate 780766307
|
||||
host_mem_usage 284536
|
||||
host_seconds 1134.49
|
||||
sim_insts 826847304
|
||||
sim_ops 1530082521
|
||||
system.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000
|
||||
system.physmem.bytes_read::cpu.inst 8546485088
|
||||
system.physmem.bytes_read::cpu.data 2285527276
|
||||
system.physmem.bytes_read::total 10832012364
|
||||
system.physmem.bytes_inst_read::cpu.inst 8546485088
|
||||
system.physmem.bytes_inst_read::total 8546485088
|
||||
system.physmem.bytes_written::cpu.data 991837474
|
||||
system.physmem.bytes_written::total 991837474
|
||||
system.physmem.num_reads::cpu.inst 1068310636
|
||||
system.physmem.num_reads::cpu.data 384083342
|
||||
system.physmem.num_reads::total 1452393978
|
||||
system.physmem.num_writes::cpu.data 149158211
|
||||
system.physmem.num_writes::total 149158211
|
||||
system.physmem.bw_read::cpu.inst 9648618554
|
||||
system.physmem.bw_read::cpu.data 2580263190
|
||||
system.physmem.bw_read::total 12228881744
|
||||
system.physmem.bw_inst_read::cpu.inst 9648618554
|
||||
system.physmem.bw_inst_read::total 9648618554
|
||||
system.physmem.bw_write::cpu.data 1119742368
|
||||
system.physmem.bw_write::total 1119742368
|
||||
system.physmem.bw_total::cpu.inst 9648618554
|
||||
system.physmem.bw_total::cpu.data 3700005559
|
||||
system.physmem.bw_total::total 13348624112
|
||||
system.pwrStateResidencyTicks::UNDEFINED 885772926000
|
||||
system.cpu_clk_domain.clock 500
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000
|
||||
system.cpu.apic_clk_domain.clock 8000
|
||||
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000
|
||||
system.cpu.workload.numSyscalls 551
|
||||
system.cpu.pwrStateResidencyTicks::ON 885772926000
|
||||
system.cpu.numCycles 1771545853
|
||||
system.cpu.numWorkItemsStarted 0
|
||||
system.cpu.numWorkItemsCompleted 0
|
||||
system.cpu.committedInsts 826847304
|
||||
system.cpu.committedOps 1530082521
|
||||
system.cpu.num_int_alu_accesses 1527470226
|
||||
system.cpu.num_fp_alu_accesses 0
|
||||
system.cpu.num_func_calls 35346287
|
||||
system.cpu.num_conditional_control_insts 92881952
|
||||
system.cpu.num_int_insts 1527470226
|
||||
system.cpu.num_fp_insts 0
|
||||
system.cpu.num_int_register_reads 3298246119
|
||||
system.cpu.num_int_register_writes 1240060586
|
||||
system.cpu.num_fp_register_reads 0
|
||||
system.cpu.num_fp_register_writes 0
|
||||
system.cpu.num_cc_register_reads 562449682
|
||||
system.cpu.num_cc_register_writes 376900986
|
||||
system.cpu.num_mem_refs 533241508
|
||||
system.cpu.num_load_insts 384083313
|
||||
system.cpu.num_store_insts 149158195
|
||||
system.cpu.num_idle_cycles 0
|
||||
system.cpu.num_busy_cycles 1771545853
|
||||
system.cpu.not_idle_fraction 1
|
||||
system.cpu.idle_fraction 0
|
||||
system.cpu.Branches 149981740
|
||||
system.cpu.op_class::No_OpClass 2048202 0.13% 0.13%
|
||||
system.cpu.op_class::IntAlu 989691029 64.68% 64.82%
|
||||
system.cpu.op_class::IntMult 306834 0.02% 64.84%
|
||||
system.cpu.op_class::IntDiv 4794948 0.31% 65.15%
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatMult 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdMult 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdShift 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15%
|
||||
system.cpu.op_class::MemRead 384083313 25.10% 90.25%
|
||||
system.cpu.op_class::MemWrite 149158195 9.75% 100.00%
|
||||
system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
|
||||
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00%
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
|
||||
system.cpu.op_class::total 1530082521
|
||||
system.membus.snoop_filter.tot_requests 0
|
||||
system.membus.snoop_filter.hit_single_requests 0
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000
|
||||
system.membus.trans_dist::ReadReq 1452393978
|
||||
system.membus.trans_dist::ReadResp 1452393978
|
||||
system.membus.trans_dist::WriteReq 149158211
|
||||
system.membus.trans_dist::WriteResp 149158211
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272
|
||||
system.membus.pkt_count_system.cpu.icache_port::total 2136621272
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106
|
||||
system.membus.pkt_count_system.cpu.dcache_port::total 1066483106
|
||||
system.membus.pkt_count::total 3203104378
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088
|
||||
system.membus.pkt_size_system.cpu.icache_port::total 8546485088
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750
|
||||
system.membus.pkt_size_system.cpu.dcache_port::total 3277364750
|
||||
system.membus.pkt_size::total 11823849838
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 1601552189
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 1601552189 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 1601552189
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,432 +0,0 @@
|
||||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
eventq_index=0
|
||||
full_system=false
|
||||
sim_quantum=0
|
||||
time_sync_enable=false
|
||||
time_sync_period=100000000000
|
||||
time_sync_spin_threshold=100000000
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=
|
||||
kernel_addr_check=true
|
||||
kvm_vm=Null
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=
|
||||
memories=system.physmem
|
||||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
readfile=
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
work_cpus_ckpt_count=0
|
||||
work_end_ckpt_count=0
|
||||
work_end_exit_count=0
|
||||
work_item_id=-1
|
||||
system_port=system.membus.slave[0]
|
||||
|
||||
[system.clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=1000
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
|
||||
branchPred=Null
|
||||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
eventq_index=0
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
interrupts=system.cpu.interrupts
|
||||
isa=system.cpu.isa
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
syscallRetryLatency=10000
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
icache_port=system.cpu.icache.cpu_side
|
||||
|
||||
[system.cpu.apic_clk_domain]
|
||||
type=DerivedClockDomain
|
||||
clk_divider=16
|
||||
clk_domain=system.cpu_clk_domain
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=262144
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.dcache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.dcache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[1]
|
||||
|
||||
[system.cpu.dcache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=262144
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.dtb.walker
|
||||
|
||||
[system.cpu.dtb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
[system.cpu.icache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=2
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
sequential_access=false
|
||||
size=131072
|
||||
system=system
|
||||
tag_latency=2
|
||||
tags=system.cpu.icache.tags
|
||||
tgts_per_mshr=20
|
||||
write_buffers=8
|
||||
writeback_clean=true
|
||||
cpu_side=system.cpu.icache_port
|
||||
mem_side=system.cpu.toL2Bus.slave[0]
|
||||
|
||||
[system.cpu.icache.tags]
|
||||
type=LRU
|
||||
assoc=2
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=2
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=131072
|
||||
tag_latency=2
|
||||
|
||||
[system.cpu.interrupts]
|
||||
type=X86LocalApic
|
||||
clk_domain=system.cpu.apic_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
int_latency=1000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=2305843009213693952
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
int_master=system.membus.slave[2]
|
||||
int_slave=system.membus.master[2]
|
||||
pio=system.membus.master[1]
|
||||
|
||||
[system.cpu.isa]
|
||||
type=X86ISA
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
children=walker
|
||||
eventq_index=0
|
||||
size=64
|
||||
walker=system.cpu.itb.walker
|
||||
|
||||
[system.cpu.itb.walker]
|
||||
type=X86PagetableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
num_squash_per_cycle=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
system=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=Cache
|
||||
children=tags
|
||||
addr_ranges=0:18446744073709551615:0:0:0:0
|
||||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
system=system
|
||||
tag_latency=20
|
||||
tags=system.cpu.l2cache.tags
|
||||
tgts_per_mshr=12
|
||||
write_buffers=8
|
||||
writeback_clean=false
|
||||
cpu_side=system.cpu.toL2Bus.master[0]
|
||||
mem_side=system.membus.slave[1]
|
||||
|
||||
[system.cpu.l2cache.tags]
|
||||
type=LRU
|
||||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
data_latency=20
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=2097152
|
||||
tag_latency=20
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=32
|
||||
master=system.cpu.l2cache.cpu_side
|
||||
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
|
||||
|
||||
[system.cpu.toL2Bus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=0
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
eventq_index=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=Process
|
||||
cmd=parser 2.1.dict -batch
|
||||
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
|
||||
drivers=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
eventq_index=0
|
||||
executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser
|
||||
gid=100
|
||||
input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
|
||||
kvmInSE=false
|
||||
maxStackSize=67108864
|
||||
output=cout
|
||||
pgid=100
|
||||
pid=100
|
||||
ppid=0
|
||||
simpoint=114600000000
|
||||
system=system
|
||||
uid=100
|
||||
useArchPT=false
|
||||
|
||||
[system.cpu_clk_domain]
|
||||
type=SrcClockDomain
|
||||
clock=500
|
||||
domain_id=-1
|
||||
eventq_index=0
|
||||
init_perf_level=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.dvfs_handler]
|
||||
type=DVFSHandler
|
||||
domains=
|
||||
enable=false
|
||||
eventq_index=0
|
||||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000000
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
width=16
|
||||
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
|
||||
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
kvm_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:134217727:0:0:0:0
|
||||
port=system.membus.master[0]
|
||||
|
||||
[system.voltage_domain]
|
||||
type=VoltageDomain
|
||||
eventq_index=0
|
||||
voltage=1.000000
|
||||
|
||||
@@ -1,6 +0,0 @@
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
info: Increasing stack size by one page.
|
||||
@@ -1,71 +0,0 @@
|
||||
Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout
|
||||
Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Apr 3 2017 19:05:53
|
||||
gem5 started Apr 3 2017 19:06:22
|
||||
gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87196
|
||||
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-timing
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
||||
Reading the dictionary files: *************************************************
|
||||
58924 words stored in 3784810 bytes
|
||||
|
||||
|
||||
Welcome to the Link Parser -- Version 2.1
|
||||
|
||||
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
|
||||
|
||||
Processing sentences in batch mode
|
||||
|
||||
Echoing of input sentence turned on.
|
||||
* as had expected the party to be a success , it was a success
|
||||
* do you know where John 's
|
||||
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
|
||||
* how fast the program is it
|
||||
* I am wondering whether to invite to the party
|
||||
* I gave him for his birthday it
|
||||
* I thought terrible after our discussion
|
||||
* I wonder how much money have you earned
|
||||
* Janet who is an expert on dogs helped me choose one
|
||||
* she interviewed more programmers than was hired
|
||||
* such flowers are found chiefly particularly in Europe
|
||||
* the dogs some of which were very large ran after the man
|
||||
* the man whom I play tennis is here
|
||||
* there is going to be an important meeting January
|
||||
* to pretend that our program is usable in its current form would be happy
|
||||
* we're thinking about going to a movie this theater
|
||||
* which dog you said you chased
|
||||
- also invited to the meeting were several prominent scientists
|
||||
- he ran home so quickly that his mother could hardly believe he had called from school
|
||||
- so many people attended that they spilled over into several neighboring fields
|
||||
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
|
||||
: Grace may not be possible to fix the problem
|
||||
any program as good as ours should be useful
|
||||
biochemically , I think the experiment has a lot of problems
|
||||
Fred has had five years of experience as a programmer
|
||||
he is looking for another job
|
||||
how did John do it
|
||||
how many more people do you think will come
|
||||
how much more spilled
|
||||
I have more money than John has time
|
||||
I made it clear that I was angry
|
||||
I wonder how John did it
|
||||
I wonder how much more quickly he ran
|
||||
invite John and whoever else you want to invite
|
||||
it is easier to ignore the problem than it is to solve it
|
||||
many who initially supported Thomas later changed their minds
|
||||
neither Mary nor Louise are coming to the party
|
||||
she interviewed more programmers than were hired
|
||||
telling Joe that Sue was coming to the party would create a real problem
|
||||
the man with whom I play tennis is here
|
||||
there is a dog in the park
|
||||
this is not the man we know and love
|
||||
we like to eat at restaurants , usually on weekends
|
||||
what did John say he thought you should do
|
||||
about 2 million people attended
|
||||
the five best costumes got prizes
|
||||
No errors!
|
||||
Exiting @ tick 1650923912500 because exiting with last active thread context
|
||||
@@ -1,546 +0,0 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.650924
|
||||
sim_ticks 1650923912500
|
||||
final_tick 1650923912500
|
||||
sim_freq 1000000000000
|
||||
host_inst_rate 500428
|
||||
host_op_rate 926043
|
||||
host_tick_rate 999178622
|
||||
host_mem_usage 295552
|
||||
host_seconds 1652.28
|
||||
sim_insts 826847304
|
||||
sim_ops 1530082521
|
||||
system.voltage_domain.voltage 1
|
||||
system.clk_domain.clock 1000
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500
|
||||
system.physmem.bytes_read::cpu.inst 115968
|
||||
system.physmem.bytes_read::cpu.data 24312256
|
||||
system.physmem.bytes_read::total 24428224
|
||||
system.physmem.bytes_inst_read::cpu.inst 115968
|
||||
system.physmem.bytes_inst_read::total 115968
|
||||
system.physmem.bytes_written::writebacks 18812864
|
||||
system.physmem.bytes_written::total 18812864
|
||||
system.physmem.num_reads::cpu.inst 1812
|
||||
system.physmem.num_reads::cpu.data 379879
|
||||
system.physmem.num_reads::total 381691
|
||||
system.physmem.num_writes::writebacks 293951
|
||||
system.physmem.num_writes::total 293951
|
||||
system.physmem.bw_read::cpu.inst 70244
|
||||
system.physmem.bw_read::cpu.data 14726455
|
||||
system.physmem.bw_read::total 14796699
|
||||
system.physmem.bw_inst_read::cpu.inst 70244
|
||||
system.physmem.bw_inst_read::total 70244
|
||||
system.physmem.bw_write::writebacks 11395355
|
||||
system.physmem.bw_write::total 11395355
|
||||
system.physmem.bw_total::writebacks 11395355
|
||||
system.physmem.bw_total::cpu.inst 70244
|
||||
system.physmem.bw_total::cpu.data 14726455
|
||||
system.physmem.bw_total::total 26192054
|
||||
system.pwrStateResidencyTicks::UNDEFINED 1650923912500
|
||||
system.cpu_clk_domain.clock 500
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500
|
||||
system.cpu.apic_clk_domain.clock 8000
|
||||
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500
|
||||
system.cpu.workload.numSyscalls 551
|
||||
system.cpu.pwrStateResidencyTicks::ON 1650923912500
|
||||
system.cpu.numCycles 3301847825
|
||||
system.cpu.numWorkItemsStarted 0
|
||||
system.cpu.numWorkItemsCompleted 0
|
||||
system.cpu.committedInsts 826847304
|
||||
system.cpu.committedOps 1530082521
|
||||
system.cpu.num_int_alu_accesses 1527470226
|
||||
system.cpu.num_fp_alu_accesses 0
|
||||
system.cpu.num_func_calls 35346287
|
||||
system.cpu.num_conditional_control_insts 92881952
|
||||
system.cpu.num_int_insts 1527470226
|
||||
system.cpu.num_fp_insts 0
|
||||
system.cpu.num_int_register_reads 3298246119
|
||||
system.cpu.num_int_register_writes 1240060586
|
||||
system.cpu.num_fp_register_reads 0
|
||||
system.cpu.num_fp_register_writes 0
|
||||
system.cpu.num_cc_register_reads 562449682
|
||||
system.cpu.num_cc_register_writes 376900986
|
||||
system.cpu.num_mem_refs 533241508
|
||||
system.cpu.num_load_insts 384083313
|
||||
system.cpu.num_store_insts 149158195
|
||||
system.cpu.num_idle_cycles 0
|
||||
system.cpu.num_busy_cycles 3301847825
|
||||
system.cpu.not_idle_fraction 1
|
||||
system.cpu.idle_fraction 0
|
||||
system.cpu.Branches 149981740
|
||||
system.cpu.op_class::No_OpClass 2048202 0.13% 0.13%
|
||||
system.cpu.op_class::IntAlu 989691029 64.68% 64.82%
|
||||
system.cpu.op_class::IntMult 306834 0.02% 64.84%
|
||||
system.cpu.op_class::IntDiv 4794948 0.31% 65.15%
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatMult 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatMultAcc 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatMisc 0 0.00% 65.15%
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdMult 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdShift 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15%
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15%
|
||||
system.cpu.op_class::MemRead 384083313 25.10% 90.25%
|
||||
system.cpu.op_class::MemWrite 149158195 9.75% 100.00%
|
||||
system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
|
||||
system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00%
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
|
||||
system.cpu.op_class::total 1530082521
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500
|
||||
system.cpu.dcache.tags.replacements 2517016
|
||||
system.cpu.dcache.tags.tagsinuse 4086.382570
|
||||
system.cpu.dcache.tags.total_refs 530720441
|
||||
system.cpu.dcache.tags.sampled_refs 2521112
|
||||
system.cpu.dcache.tags.avg_refs 210.510458
|
||||
system.cpu.dcache.tags.warmup_cycle 8250925500
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997652
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997652
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 29
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1
|
||||
system.cpu.dcache.tags.tag_accesses 1069004218
|
||||
system.cpu.dcache.tags.data_accesses 1069004218
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382353600
|
||||
system.cpu.dcache.ReadReq_hits::total 382353600
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148366841
|
||||
system.cpu.dcache.WriteReq_hits::total 148366841
|
||||
system.cpu.dcache.demand_hits::cpu.data 530720441
|
||||
system.cpu.dcache.demand_hits::total 530720441
|
||||
system.cpu.dcache.overall_hits::cpu.data 530720441
|
||||
system.cpu.dcache.overall_hits::total 530720441
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1729742
|
||||
system.cpu.dcache.ReadReq_misses::total 1729742
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 791370
|
||||
system.cpu.dcache.WriteReq_misses::total 791370
|
||||
system.cpu.dcache.demand_misses::cpu.data 2521112
|
||||
system.cpu.dcache.demand_misses::total 2521112
|
||||
system.cpu.dcache.overall_misses::cpu.data 2521112
|
||||
system.cpu.dcache.overall_misses::total 2521112
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 31154171500
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20614263500
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 51768435000
|
||||
system.cpu.dcache.demand_miss_latency::total 51768435000
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 51768435000
|
||||
system.cpu.dcache.overall_miss_latency::total 51768435000
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 384083342
|
||||
system.cpu.dcache.ReadReq_accesses::total 384083342
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149158211
|
||||
system.cpu.dcache.WriteReq_accesses::total 149158211
|
||||
system.cpu.dcache.demand_accesses::cpu.data 533241553
|
||||
system.cpu.dcache.demand_accesses::total 533241553
|
||||
system.cpu.dcache.overall_accesses::cpu.data 533241553
|
||||
system.cpu.dcache.overall_accesses::total 533241553
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004504
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005306
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.004728
|
||||
system.cpu.dcache.demand_miss_rate::total 0.004728
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004728
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004728
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 20533.968741
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 20533.968741
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0
|
||||
system.cpu.dcache.blocked::no_mshrs 0
|
||||
system.cpu.dcache.blocked::no_targets 0
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.dcache.writebacks::writebacks 2324919
|
||||
system.cpu.dcache.writebacks::total 2324919
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1729742
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 791370
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2521112
|
||||
system.cpu.dcache.demand_mshr_misses::total 2521112
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2521112
|
||||
system.cpu.dcache.overall_mshr_misses::total 2521112
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 49247323000
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 49247323000
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.004728
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.004728
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500
|
||||
system.cpu.icache.tags.replacements 1253
|
||||
system.cpu.icache.tags.tagsinuse 881.361666
|
||||
system.cpu.icache.tags.total_refs 1068307823
|
||||
system.cpu.icache.tags.sampled_refs 2814
|
||||
system.cpu.icache.tags.avg_refs 379640.306681
|
||||
system.cpu.icache.tags.warmup_cycle 0
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.430352
|
||||
system.cpu.icache.tags.occ_percent::total 0.430352
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1561
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 38
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 1
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 7
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 8
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1507
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207
|
||||
system.cpu.icache.tags.tag_accesses 2136624088
|
||||
system.cpu.icache.tags.data_accesses 2136624088
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500
|
||||
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|
||||
system.cpu.toL2Bus.respLayer0.occupancy 4221000
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3781668000
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2
|
||||
system.membus.snoop_filter.tot_requests 729250
|
||||
system.membus.snoop_filter.hit_single_requests 347559
|
||||
system.membus.snoop_filter.hit_multi_requests 0
|
||||
system.membus.snoop_filter.tot_snoops 0
|
||||
system.membus.snoop_filter.hit_single_snoops 0
|
||||
system.membus.snoop_filter.hit_multi_snoops 0
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500
|
||||
system.membus.trans_dist::ReadResp 175162
|
||||
system.membus.trans_dist::WritebackDirty 293951
|
||||
system.membus.trans_dist::CleanEvict 53608
|
||||
system.membus.trans_dist::ReadExReq 206529
|
||||
system.membus.trans_dist::ReadExResp 206529
|
||||
system.membus.trans_dist::ReadSharedReq 175162
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941
|
||||
system.membus.pkt_count::total 1110941
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088
|
||||
system.membus.pkt_size::total 43241088
|
||||
system.membus.snoops 0
|
||||
system.membus.snoopTraffic 0
|
||||
system.membus.snoop_fanout::samples 381691
|
||||
system.membus.snoop_fanout::mean 0
|
||||
system.membus.snoop_fanout::stdev 0
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00%
|
||||
system.membus.snoop_fanout::0 381691 100.00% 100.00%
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00%
|
||||
system.membus.snoop_fanout::min_value 0
|
||||
system.membus.snoop_fanout::max_value 0
|
||||
system.membus.snoop_fanout::total 381691
|
||||
system.membus.reqLayer0.occupancy 1905079500
|
||||
system.membus.reqLayer0.utilization 0.1
|
||||
system.membus.respLayer1.occupancy 1908455000
|
||||
system.membus.respLayer1.utilization 0.1
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
@@ -1,33 +0,0 @@
|
||||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Korey Sewell
|
||||
|
||||
m5.util.addToPath('../configs/common')
|
||||
from cpu2000 import parser
|
||||
|
||||
workload = parser(isa, opsys, 'mdred')
|
||||
root.system.cpu[0].workload = workload.makeProcess()
|
||||
Reference in New Issue
Block a user