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misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

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With this commit we replace every TLB pointer stored in the
cpu model with a BaseMMU pointer.

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I4932a32f68582b25cd252b5420b54d6a40ee15b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34976
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-12-13 00:18:47 +00:00
parent 85a36581d4
commit 330a5f7bad
48 changed files with 230 additions and 183 deletions
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4
configs/common/Options.py
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@@ -364,8 +364,8 @@ def addCommonOptions(parser):
parser.add_option("--stats-root", action="append", default=[], help=
"If given, dump only stats of objects under the given SimObject. "
"SimObjects are identified with Python notation as in: "
"system.cpu[0].dtb. All elements of an array can be selected at "
"once with: system.cpu[:].dtb. If given multiple times, dump stats "
"system.cpu[0].mmu. All elements of an array can be selected at "
"once with: system.cpu[:].mmu. If given multiple times, dump stats "
"that are present under any of the roots. If not given, dump all "
"stats. "
)