misc: merge branch 'release-staging-v19.0.0.0' into develop

Change-Id: I8430c6717697563386d165a40a0d080b0d18832e

src/arch/x86/mmapped_ipr.hh

@@ -44,6 +44,7 @@
  * ISA-specific helper functions for memory mapped IPR accesses.
  */
 
+#include "arch/x86/pseudo_inst_abi.hh"
 #include "arch/x86/regs/misc.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
@@ -61,7 +62,7 @@ namespace X86ISA
         if (m5opRange.contains(addr)) {
             uint8_t func;
             PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
-            uint64_t ret = PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
+            uint64_t ret = PseudoInst::pseudoInst<X86PseudoInstABI>(tc, func);
             pkt->setLE(ret);
         } else {
             Addr offset = addr & mask(3);
@@ -82,7 +83,7 @@ namespace X86ISA
         if (m5opRange.contains(addr)) {
             uint8_t func;
             PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
-            PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
+            PseudoInst::pseudoInst<X86PseudoInstABI>(tc, func);
         } else {
             Addr offset = addr & mask(3);
             MiscRegIndex index = (MiscRegIndex)(addr / sizeof(RegVal));

src/arch/x86/pseudo_inst_abi.hh

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2020 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/x86/registers.hh"
+#include "sim/guest_abi.hh"
+
+struct X86PseudoInstABI
+{
+    using Position = int;
+};
+
+namespace GuestABI
+{
+
+template <typename T>
+struct Result<X86PseudoInstABI, T>
+{
+    static void
+    store(ThreadContext *tc, const T &ret)
+    {
+        // This assumes that all pseudo ops have their return value set
+        // by the pseudo op instruction. This may need to be revisited if we
+        // modify the pseudo op ABI in util/m5/m5op_x86.S
+        tc->setIntReg(X86ISA::INTREG_RAX, ret);
+    }
+};
+
+template <>
+struct Argument<X86PseudoInstABI, uint64_t>
+{
+    static uint64_t
+    get(ThreadContext *tc, X86PseudoInstABI::Position &position)
+    {
+        // The first 6 integer arguments are passed in registers, the rest
+        // are passed on the stack.
+
+        panic_if(position >= 6, "Too many psuedo inst arguments.");
+
+        using namespace X86ISA;
+
+        const int int_reg_map[] = {
+            INTREG_RDI, INTREG_RSI, INTREG_RDX,
+            INTREG_RCX, INTREG_R8, INTREG_R9
+        };
+
+        return tc->readIntReg(int_reg_map[position++]);
+    }
+};
+
+} // namespace GuestABI

util/m5/m5op_x86.S

@@ -28,6 +28,14 @@
 
 #include <gem5/asm/generic/m5ops.h>
 
+/*
+  Note: The ABI for pseudo ops using the M5OP_ADDR is defined in
+  src/arch/x86/pseudo_inst_abi.hh. If the ABI is changed below, it's likely
+  that the ABI in the arch directory will also need to be updated.
+
+  The ABI for the magic instruction-based pseudo ops is not affected by this.
+*/
+
 #if defined(M5OP_ADDR) && defined(M5OP_PIC)
 /* Use the memory mapped m5op interface */
 #define TWO_BYTE_OP(name, number)         \