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change readPC() + 4 to readNextPC() and the same for NNPC ...

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arch/mips/isa/decoder.isa:
    remove useless cout statements
arch/mips/isa_traits.hh:
    space

--HG--
extra : convert_revision : 8b8cf5df6fc3eb92598360343eb887c35cda202d
This commit is contained in:
Korey Sewell
2006-04-27 16:44:12 -04:00
parent 07d4ad4dbe
commit 316f1f3239
3 changed files with 17 additions and 12 deletions
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4
arch/isa_parser.py
View File

@@ -1334,7 +1334,7 @@ class NPCOperand(Operand):
return ''
def makeRead(self):
return '%s = xc->readPC() + 4;\n' % self.base_name
return '%s = xc->readNextPC();\n' % self.base_name
def makeWrite(self):
return 'xc->setNextPC(%s);\n' % self.base_name
@@ -1344,7 +1344,7 @@ class NNPCOperand(Operand):
return ''
def makeRead(self):
return '%s = xc->readPC() + 8;\n' % self.base_name
return '%s = xc->readNextNPC();\n' % self.base_name
def makeWrite(self):
return 'xc->setNextNPC(%s);\n' % self.base_name

22
arch/mips/isa/decoder.isa
View File

@@ -407,7 +407,6 @@ decode OPCODE_HI default Unknown::unknown() {
format System {
0x2: cfc1({{
std::cout << "FP Control Reg " << FS << "accessed." << std::endl;
uint32_t fcsr_reg = xc->readMiscReg(FCSR);
switch (FS)
@@ -434,8 +433,6 @@ decode OPCODE_HI default Unknown::unknown() {
}});
0x6: ctc1({{
std::cout << "FP Control Reg " << FS << "accessed." << std::endl;
uint32_t fcsr_reg = xc->readMiscReg(FCSR);
uint32_t temp;
switch (FS)
@@ -553,22 +550,27 @@ decode OPCODE_HI default Unknown::unknown() {
format FloatOp {
0x1: cvt_d_s({{
int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
//int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(,DOUBLE_TO_SINGLE);
}});
0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
0x4: cvt_w_s({{
//int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
}});
}
//only legal for 64 bit
format Float64Op {
0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
0x5: cvt_l_s({{
//int rnd_mode = xc->readMiscReg(FCSR);
Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
}});
0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }});
0x6: cvt_ps_s({{
//int rnd_mode = xc->readMiscReg(FCSR);
/*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/
}});
}
}
}

3
arch/mips/isa_traits.hh
View File

@@ -253,6 +253,7 @@ namespace MipsISA
uint32_t result32;
memcpy(&result32, regSpace + 4 * floatReg, FloatRegSize);
return htog(result32);
case DoubleWidth:
uint64_t result64;
memcpy(&result64, regSpace + 4 * floatReg, DoubleRegSize);
@@ -314,6 +315,8 @@ namespace MipsISA
return NoFault;
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);