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SPARC: Clean up of privileged instructions.

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--HG--
extra : convert_revision : 1fb055a7d186a3e9dff46f1c1b46bad6bcd00562
This commit is contained in:
Gabe Black
2007-09-25 20:09:25 -07:00
parent b896ad584b
commit 306b5c6b5b
2 changed files with 49 additions and 83 deletions
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86
src/arch/sparc/isa/decoder.isa
View File

@@ -313,7 +313,7 @@ decode OP default Unknown::unknown()
//1 should cause an illegal instruction exception
0x02: NoPriv::rdccr({{Rd = Ccr;}});
0x03: NoPriv::rdasi({{Rd = Asi;}});
0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
0x05: NoPriv::rdpc({{
if(Pstate<3:>)
Rd = (xc->readPC())<31:0>;
@@ -329,7 +329,7 @@ decode OP default Unknown::unknown()
0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);
}
0x10: Priv::rdpcr({{Rd = Pcr;}});
0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
//0x12 should cause an illegal instruction exception
0x13: NoPriv::rdgsr({{
fault = checkFpEnableFault(xc);
@@ -340,7 +340,7 @@ decode OP default Unknown::unknown()
//0x14-0x15 should cause an illegal instruction exception
0x16: Priv::rdsoftint({{Rd = Softint;}});
0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}});
0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
0x1A: Priv::rdstrand_sts_reg({{
if(Pstate<2:> && !Hpstate<2:>)
@@ -354,11 +354,7 @@ decode OP default Unknown::unknown()
}
0x29: decode RS1 {
0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
0x01: HPriv::rdhprhtstate({{
if(Tl == 0)
return new IllegalInstruction;
Rd = Htstate;
}});
0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true);
//0x02 should cause an illegal instruction exception
0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
//0x04 should cause an illegal instruction exception
@@ -368,26 +364,10 @@ decode OP default Unknown::unknown()
0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
}
0x2A: decode RS1 {
0x00: Priv::rdprtpc({{
if(Tl == 0)
return new IllegalInstruction;
Rd = Tpc;
}});
0x01: Priv::rdprtnpc({{
if(Tl == 0)
return new IllegalInstruction;
Rd = Tnpc;
}});
0x02: Priv::rdprtstate({{
if(Tl == 0)
return new IllegalInstruction;
Rd = Tstate;
}});
0x03: Priv::rdprtt({{
if(Tl == 0)
return new IllegalInstruction;
Rd = Tt;
}});
0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true);
0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true);
0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true);
0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true);
0x04: Priv::rdprtick({{Rd = Tick;}});
0x05: Priv::rdprtba({{Rd = Tba;}});
0x06: Priv::rdprpstate({{Rd = Pstate;}});
@@ -455,7 +435,7 @@ decode OP default Unknown::unknown()
//0x07-0x0E should cause an illegal instruction exception
0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
//0x12 should cause an illegal instruction exception
0x13: NoPriv::wrgsr({{
if(Fprs<2:> == 0 || Pstate<4:> == 0)
@@ -503,30 +483,14 @@ decode OP default Unknown::unknown()
}});
}
0x32: decode RD {
0x00: Priv::wrprtpc({{
if(Tl == 0)
return new IllegalInstruction;
else
Tpc = Rs1 ^ Rs2_or_imm13;
}});
0x01: Priv::wrprtnpc({{
if(Tl == 0)
return new IllegalInstruction;
else
Tnpc = Rs1 ^ Rs2_or_imm13;
}});
0x02: Priv::wrprtstate({{
if(Tl == 0)
return new IllegalInstruction;
else
Tstate = Rs1 ^ Rs2_or_imm13;
}});
0x03: Priv::wrprtt({{
if(Tl == 0)
return new IllegalInstruction;
else
Tt = Rs1 ^ Rs2_or_imm13;
}});
0x00: Priv::wrprtpc(
{{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
0x01: Priv::wrprtnpc(
{{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
0x02: Priv::wrprtstate(
{{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
0x03: Priv::wrprtt(
{{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
@@ -554,11 +518,8 @@ decode OP default Unknown::unknown()
}
0x33: decode RD {
0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
0x01: HPriv::wrhprhtstate({{
if(Tl == 0)
return new IllegalInstruction;
Htstate = Rs1 ^ Rs2_or_imm13;
}});
0x01: HPriv::wrhprhtstate(
{{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
//0x02 should cause an illegal instruction exception
0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
//0x04 should cause an illegal instruction exception
@@ -1130,9 +1091,6 @@ decode OP default Unknown::unknown()
}});
0x3E: decode FCN {
0x0: Priv::done({{
if(Tl == 0)
return new IllegalInstruction;
Cwp = Tstate<4:0>;
Pstate = Tstate<20:8>;
Asi = Tstate<31:24>;
@@ -1142,10 +1100,8 @@ decode OP default Unknown::unknown()
NPC = Tnpc;
NNPC = Tnpc + 4;
Tl = Tl - 1;
}});
}}, checkTl=true);
0x1: Priv::retry({{
if(Tl == 0)
return new IllegalInstruction;
Cwp = Tstate<4:0>;
Pstate = Tstate<20:8>;
Asi = Tstate<31:24>;
@@ -1155,7 +1111,7 @@ decode OP default Unknown::unknown()
NPC = Tpc;
NNPC = Tnpc;
Tl = Tl - 1;
}});
}}, checkTl=true);
}
}
}

46
src/arch/sparc/isa/formats/priv.isa
View File

@@ -1,4 +1,4 @@
// Copyright (c) 2006 The Regents of The University of Michigan
// Copyright (c) 2006-2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -207,6 +207,9 @@ def template PrivExecute {{
if(%(check)s)
return new PrivilegedAction;
if(%(tlCheck)s)
return new IllegalInstruction;
Fault fault = NoFault;
%(code)s;
%(op_wb)s;
@@ -215,7 +218,7 @@ def template PrivExecute {{
}};
let {{
def doPrivFormat(code, checkCode, name, Name, opt_flags):
def doPrivFormat(code, checkCode, name, Name, tlCheck, opt_flags):
(usesImm, code, immCode,
rString, iString) = splitOutImm(code)
#If these are rd, rdpr, rdhpr, wr, wrpr, or wrhpr instructions,
@@ -236,7 +239,8 @@ let {{
regBase = 'WrPriv'
break
iop = InstObjParams(name, Name, regBase,
{"code": code, "check": checkCode, "reg_name": regName},
{"code": code, "check": checkCode,
"tlCheck": tlCheck, "reg_name": regName},
opt_flags)
header_output = BasicDeclare.subst(iop)
if regName == '':
@@ -246,7 +250,8 @@ let {{
exec_output = PrivExecute.subst(iop)
if usesImm:
imm_iop = InstObjParams(name, Name + 'Imm', regBase + 'Imm',
{"code": immCode, "check": checkCode, "reg_name": regName},
{"code": immCode, "check": checkCode,
"tlCheck": tlCheck, "reg_name": regName},
opt_flags)
header_output += BasicDeclare.subst(imm_iop)
if regName == '':
@@ -260,34 +265,39 @@ let {{
return (header_output, decoder_output, exec_output, decode_block)
}};
def format Priv(code, *opt_flags) {{
checkCode = "!(Pstate<2:> || Hpstate<2:>)"
def format Priv(code, extraCond=true, checkTl=false, *opt_flags) {{
checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCond
if checkTl != "false":
tlCheck = "Tl == 0"
else:
tlCheck = "false"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags)
checkCode, name, Name, tlCheck, opt_flags)
}};
def format NoPriv(code, *opt_flags) {{
def format NoPriv(code, checkTl=false, *opt_flags) {{
#Instructions which use this format don't really check for
#any particular mode, but the disassembly is performed
#using the control registers actual name
checkCode = "false"
if checkTl != "false":
tlCheck = "Tl == 0"
else:
tlCheck = "false"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags)
checkCode, name, Name, tlCheck, opt_flags)
}};
def format PrivCheck(code, extraCheckCode, *opt_flags) {{
checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCheckCode
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags)
}};
def format HPriv(code, *opt_flags) {{
def format HPriv(code, checkTl=false, *opt_flags) {{
checkCode = "!Hpstate<2:2>"
if checkTl != "false":
tlCheck = "Tl == 0"
else:
tlCheck = "false"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags)
checkCode, name, Name, tlCheck, opt_flags)
}};