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ARM: Take advantage of new PCState syntax.

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This commit is contained in:
Gabe Black
2010-12-09 14:45:17 -08:00
parent 24c5b5925d
commit 2ff3e6b399
6 changed files with 198 additions and 189 deletions
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55
src/arch/arm/isa/insts/branch.isa
View File

@@ -46,17 +46,14 @@ let {{
# B, BL
for (mnem, link) in (("b", False), ("bl", True)):
bCode = '''
ArmISA::PCState pc = PCS;
Addr curPc = pc.instPC();
pc.instNPC((uint32_t)(curPc + imm));
PCS = pc;
NPC = (uint32_t)(PC + imm);
'''
if (link):
bCode += '''
if (pc.thumb())
LR = curPc | 1;
if (Thumb)
LR = PC | 1;
else
LR = curPc - 4;
LR = PC - 4;
'''
bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
@@ -68,12 +65,9 @@ let {{
# BX, BLX
blxCode = '''
ArmISA::PCState pc = PCS;
Addr curPc M5_VAR_USED = pc.instPC();
%(link)s
// Switch modes
%(branch)s
PCS = pc;
'''
blxList = (("blx", True, True),
@@ -85,8 +79,8 @@ let {{
if imm:
Name += "Imm"
# Since we're switching ISAs, the target ISA will be the opposite
# of the current ISA. pc.thumb() is whether the target is ARM.
newPC = '(pc.thumb() ? (roundDown(curPc, 4) + imm) : (curPc + imm))'
# of the current ISA. Thumb is whether the target is ARM.
newPC = '(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
base = "BranchImmCond"
declare = BranchImmCondDeclare
constructor = BranchImmCondConstructor
@@ -101,28 +95,28 @@ let {{
// The immediate version of the blx thumb instruction
// is 32 bits wide, but "next pc" doesn't reflect that
// so we don't want to substract 2 from it at this point
if (pc.thumb())
LR = curPc | 1;
if (Thumb)
LR = PC | 1;
else
LR = curPc - 4;
LR = PC - 4;
'''
elif link:
linkStr = '''
if (pc.thumb())
LR = (curPc - 2) | 1;
if (Thumb)
LR = (PC - 2) | 1;
else
LR = curPc - 4;
LR = PC - 4;
'''
else:
linkStr = ""
if imm and link: #blx with imm
branchStr = '''
pc.nextThumb(!pc.thumb());
pc.instNPC(%(newPC)s);
NextThumb = !Thumb;
NPC = %(newPC)s;
'''
else:
branchStr = "pc.instIWNPC(%(newPC)s);"
branchStr = "IWNPC = %(newPC)s;"
branchStr = branchStr % { "newPC" : newPC }
code = blxCode % {"link": linkStr,
@@ -139,12 +133,7 @@ let {{
#CBNZ, CBZ. These are always unconditional as far as predicates
for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")):
code = '''
ArmISA::PCState pc = PCS;
Addr curPc = pc.instPC();
pc.instNPC((uint32_t)(curPc + imm));
PCS = pc;
'''
code = 'NPC = (uint32_t)(PC + imm);\n'
predTest = "Op1 %(test)s 0" % {"test": test}
iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
{"code": code, "predicate_test": predTest})
@@ -161,11 +150,7 @@ let {{
ArmISA::TLB::MustBeOne;
EA = Op1 + Op2 * 2
'''
accCode = '''
ArmISA::PCState pc = PCS;
pc.instNPC(pc.instPC() + 2 * (Mem.uh));
PCS = pc;
'''
accCode = 'NPC = PC + 2 * (Mem.uh);\n'
mnem = "tbh"
else:
eaCode = '''
@@ -174,11 +159,7 @@ let {{
ArmISA::TLB::MustBeOne;
EA = Op1 + Op2
'''
accCode = '''
ArmISA::PCState pc = PCS;
pc.instNPC(pc.instPC() + 2 * (Mem.ub));
PCS = pc;
'''
accCode = 'NPC = PC + 2 * (Mem.ub)'
mnem = "tbb"
iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
{'ea_code': eaCode,

9
src/arch/arm/isa/insts/data.isa
View File

@@ -239,10 +239,8 @@ let {{
cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
CondCodes = CondCodesMask & newCpsr;
ArmISA::PCState pc = PCS;
pc.nextThumb(((CPSR)newCpsr).t);
pc.nextJazelle(((CPSR)newCpsr).j);
PCS = pc;
NextThumb = ((CPSR)newCpsr).t;
NextJazelle = ((CPSR)newCpsr).j;
'''
buildImmDataInst(mnem + 's', code, flagType,
suffix = "ImmPclr", buildCc = False,
@@ -257,8 +255,7 @@ let {{
buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
buildImmDataInst("adr", '''
ArmISA::PCState pc = PCS;
Dest = resTemp = (pc.instPC() & ~0x3) +
Dest = resTemp = (PC & ~0x3) +
(op1 ? secondOp : -secondOp);
''')
buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")

9
src/arch/arm/isa/insts/ldr.isa
View File

@@ -105,16 +105,15 @@ let {{
accCode = '''
CPSR cpsr = Cpsr;
SCTLR sctlr = Sctlr;
ArmISA::PCState pc = PCS;
pc.instNPC(cSwap<uint32_t>(Mem.ud, cpsr.e));
// Use the version of NPC that gets set before NextThumb
pNPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
uint32_t newCpsr =
cpsrWriteByInstr(cpsr | CondCodes,
cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
pc.nextThumb(((CPSR)newCpsr).t);
pc.nextJazelle(((CPSR)newCpsr).j);
PCS = pc;
NextThumb = ((CPSR)newCpsr).t;
NextJazelle = ((CPSR)newCpsr).j;
CondCodes = CondCodesMask & newCpsr;
'''
self.codeBlobs["memacc_code"] = accCode

4
src/arch/arm/isa/insts/macromem.isa
View File

@@ -93,9 +93,7 @@ let {{
cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
CondCodes = CondCodesMask & newCpsr;
ArmISA::PCState pc = PCS;
pc.instIWNPC(cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0));
PCS = pc;
IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
'''
microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
'MicroMemOp',

29
src/arch/arm/isa/insts/misc.isa
View File

@@ -83,10 +83,8 @@ let {{
uint32_t newCpsr =
cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
ArmISA::PCState pc = PCS;
pc.nextThumb(((CPSR)newCpsr).t);
pc.nextJazelle(((CPSR)newCpsr).j);
PCS = pc;
NextThumb = ((CPSR)newCpsr).t;
NextJazelle = ((CPSR)newCpsr).j;
CondCodes = CondCodesMask & newCpsr;
'''
msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
@@ -111,10 +109,8 @@ let {{
uint32_t newCpsr =
cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
ArmISA::PCState pc = PCS;
pc.nextThumb(((CPSR)newCpsr).t);
pc.nextJazelle(((CPSR)newCpsr).j);
PCS = pc;
NextThumb = ((CPSR)newCpsr).t;
NextJazelle = ((CPSR)newCpsr).j;
CondCodes = CondCodesMask & newCpsr;
'''
msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
@@ -470,10 +466,7 @@ let {{
decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
exec_output += PredOpExecute.subst(usada8Iop)
bkptCode = '''
ArmISA::PCState pc = PCS;
return new PrefetchAbort(pc.pc(), ArmFault::DebugEvent);
'''
bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
bkptCode)
header_output += BasicDeclare.subst(bkptIop)
@@ -650,10 +643,8 @@ let {{
exec_output += PredOpExecute.subst(mcr15UserIop)
enterxCode = '''
ArmISA::PCState pc = PCS;
pc.nextThumb(true);
pc.nextJazelle(true);
PCS = pc;
NextThumb = true;
NextJazelle = true;
'''
enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
{ "code": enterxCode,
@@ -663,10 +654,8 @@ let {{
exec_output += PredOpExecute.subst(enterxIop)
leavexCode = '''
ArmISA::PCState pc = PCS;
pc.nextThumb(true);
pc.nextJazelle(false);
PCS = pc;
NextThumb = true;
NextJazelle = false;
'''
leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
{ "code": leavexCode,

281
src/arch/arm/isa/operands.isa
View File

@@ -80,133 +80,178 @@ let {{
xc->%(func)s(this, %(op_idx)s, %(final_val)s);
}
'''
#PCState operands need to have a sorting index (the number at the end)
#less than all the integer registers which might update the PC. That way
#if the flag bits of the pc state are updated and a branch happens through
#R15, the updates are layered properly and the R15 update isn't lost.
srtNormal = 5
srtCpsr = 4
srtBase = 3
srtPC = 2
srtMode = 1
srtEPC = 0
def floatReg(idx):
return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
def intReg(idx):
return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
maybePCRead, maybePCWrite)
def intRegNPC(idx):
return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
def intRegAPC(idx, id = srtNormal):
return ('IntReg', 'uw', idx, 'IsInteger', id,
maybeAlignedPCRead, maybePCWrite)
def intRegIWPC(idx):
return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
maybePCRead, maybeIWPCWrite)
def intRegAIWPC(idx):
return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
maybePCRead, maybeAIWPCWrite)
def intRegCC(idx):
return ('IntReg', 'uw', idx, None, srtNormal)
def cntrlReg(idx, id = srtNormal, type = 'uw'):
return ('ControlReg', type, idx, (None, None, 'IsControl'), id)
def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
return ('ControlReg', type, idx, None, id)
def pcStateReg(idx, id):
return ('PCState', 'uw', idx, (None, None, 'IsControl'), id)
}};
def operands {{
#Abstracted integer reg operands
'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3),
'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3),
'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 3),
'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 3),
'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 3),
'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 3),
'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 3),
'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 3),
'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 3),
'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 3),
'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 3),
'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 3),
'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 3),
'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 3),
'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 3),
'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 3),
'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 3),
'Result': ('IntReg', 'uw', 'result', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3),
'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3),
'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 3),
'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 3),
'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 3),
'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
maybePCRead, maybeIWPCWrite),
'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
maybePCRead, maybeAIWPCWrite),
'SpMode': ('IntReg', 'uw',
'intRegInMode((OperatingMode)regMode, INTREG_SP)',
'IsInteger', 3),
'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 3),
'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
maybeAlignedPCRead, maybePCWrite),
'Index': ('IntReg', 'uw', 'index', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3),
'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3),
'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 3),
'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 3),
'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 3),
'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 3),
'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 3),
'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 3),
'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 3),
'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 3),
'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 3),
'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 3),
'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 3),
'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 3),
'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 3),
'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 3),
'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 3),
'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 3),
'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3),
'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3),
'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 3),
'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 3),
'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 3),
'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 3,
maybePCRead, maybePCWrite),
'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 3,
maybePCRead, maybePCWrite),
#General Purpose Integer Reg Operands
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 3, maybePCRead, maybePCWrite),
'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 3, maybePCRead, maybePCWrite),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite),
'R7': ('IntReg', 'uw', '7', 'IsInteger', 3),
'R0': ('IntReg', 'uw', '0', 'IsInteger', 3),
'R1': ('IntReg', 'uw', '0', 'IsInteger', 3),
'R2': ('IntReg', 'uw', '1', 'IsInteger', 3),
'Rt' : ('IntReg', 'uw', 'RT', 'IsInteger', 3, maybePCRead, maybePCWrite),
'Dest': intReg('dest'),
'IWDest': intRegIWPC('dest'),
'AIWDest': intRegAIWPC('dest'),
'Dest2': intReg('dest2'),
'Result': intReg('result'),
'Base': intRegAPC('base', id = srtBase),
'Index': intReg('index'),
'Shift': intReg('shift'),
'Op1': intReg('op1'),
'Op2': intReg('op2'),
'Op3': intReg('op3'),
'Reg0': intReg('reg0'),
'Reg1': intReg('reg1'),
'Reg2': intReg('reg2'),
'Reg3': intReg('reg3'),
'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3),
'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3),
'OptCondCodes': ('IntReg', 'uw',
#Fixed index integer reg operands
'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
'LR': intRegNPC('INTREG_LR'),
'R7': intRegNPC('7'),
'R0': intRegNPC('0'),
'R1': intRegNPC('0'),
'R2': intRegNPC('1'),
#Pseudo integer condition code registers
'CondCodes': intRegCC('INTREG_CONDCODES'),
'OptCondCodes': intRegCC(
'''(condCode == COND_AL || condCode == COND_UC) ?
INTREG_ZERO : INTREG_CONDCODES''', None, 3),
'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 3),
INTREG_ZERO : INTREG_CONDCODES'''),
'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
#Abstracted floating point reg operands
'FpDest': floatReg('(dest + 0)'),
'FpDestP0': floatReg('(dest + 0)'),
'FpDestP1': floatReg('(dest + 1)'),
'FpDestP2': floatReg('(dest + 2)'),
'FpDestP3': floatReg('(dest + 3)'),
'FpDestP4': floatReg('(dest + 4)'),
'FpDestP5': floatReg('(dest + 5)'),
'FpDestP6': floatReg('(dest + 6)'),
'FpDestP7': floatReg('(dest + 7)'),
'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
'FpDest2': floatReg('(dest2 + 0)'),
'FpDest2P0': floatReg('(dest2 + 0)'),
'FpDest2P1': floatReg('(dest2 + 1)'),
'FpDest2P2': floatReg('(dest2 + 2)'),
'FpDest2P3': floatReg('(dest2 + 3)'),
'FpOp1': floatReg('(op1 + 0)'),
'FpOp1P0': floatReg('(op1 + 0)'),
'FpOp1P1': floatReg('(op1 + 1)'),
'FpOp1P2': floatReg('(op1 + 2)'),
'FpOp1P3': floatReg('(op1 + 3)'),
'FpOp1P4': floatReg('(op1 + 4)'),
'FpOp1P5': floatReg('(op1 + 5)'),
'FpOp1P6': floatReg('(op1 + 6)'),
'FpOp1P7': floatReg('(op1 + 7)'),
'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
'FpOp2': floatReg('(op2 + 0)'),
'FpOp2P0': floatReg('(op2 + 0)'),
'FpOp2P1': floatReg('(op2 + 1)'),
'FpOp2P2': floatReg('(op2 + 2)'),
'FpOp2P3': floatReg('(op2 + 3)'),
#Abstracted control reg operands
'MiscDest': cntrlReg('dest'),
'MiscOp1': cntrlReg('op1'),
#Fixed index control regs
'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
'Itstate': cntrlRegNC('MISCREG_ITSTATE', type = 'ub'),
'Spsr': cntrlRegNC('MISCREG_SPSR'),
'Fpsr': cntrlRegNC('MISCREG_FPSR'),
'Fpsid': cntrlRegNC('MISCREG_FPSID'),
'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
'Cpacr': cntrlReg('MISCREG_CPACR'),
'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
#Register fields for microops
'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, maybePCRead, maybePCWrite),
'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 3,
maybePCRead, maybeIWPCWrite),
'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 3),
'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 3, maybePCRead, maybePCWrite),
'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 3, maybePCRead, maybePCWrite),
'Ra' : intReg('ura'),
'IWRa' : intRegIWPC('ura'),
'Fa' : floatReg('ura'),
'Rb' : intReg('urb'),
'Rc' : intReg('urc'),
#Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 3),
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 2),
'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 3),
'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 3),
'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3),
'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3),
'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 3),
'FpscrQc': ('ControlReg', 'uw', 'MISCREG_FPSCR_QC', None, 3),
'FpscrExc': ('ControlReg', 'uw', 'MISCREG_FPSCR_EXC', None, 3),
'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 3),
'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 3),
'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 3),
'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 3),
#PCS needs to have a sorting index (the number at the end) less than all
#the integer registers which might update the PC. That way if the flag
#bits of the pc state are updated and a branch happens through R15, the
#updates are layered properly and the R15 update isn't lost.
'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 0)
#PCState fields
'PC': pcStateReg('instPC', srtPC),
'NPC': pcStateReg('instNPC', srtPC),
'pNPC': pcStateReg('instNPC', srtEPC),
'IWNPC': pcStateReg('instIWNPC', srtPC),
'Thumb': pcStateReg('thumb', srtPC),
'NextThumb': pcStateReg('nextThumb', srtMode),
'NextJazelle': pcStateReg('nextJazelle', srtMode),
#Register operands depending on a field in the instruction encoding. These
#should be avoided since they may not be portable across different
#encodings of the same instruction.
'Rd': intReg('RD'),
'Rm': intReg('RM'),
'Rs': intReg('RS'),
'Rn': intReg('RN'),
'Rt': intReg('RT')
}};