arch-arm: Add support for Tarmac trace-based simulation
A new InstTracer (TarmacParser) has been implemented. This tracer is parsing a pre-existing Tarmac trace file [1] while gem5 is running; it is comparing execution data together with trace data and it is dumping differences. This allows to use Tarmac format as a glue between heterogeneous simuators speaking the same Tarmac language. Kudos to Giacomo Gabrielli for writing the original tracer. [1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format Change-Id: I9b92204a149813166166adba4a7c61a248bdcac3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9381 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
44
src/arch/arm/tracers/SConscript
Normal file
44
src/arch/arm/tracers/SConscript
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@@ -0,0 +1,44 @@
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# Copyright (c) 2018 ARM Limited
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# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Giacomo Gabrielli
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# Giacomo Travaglini
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Import('*')
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if env['TARGET_ISA'] == 'arm':
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SimObject('TarmacTrace.py')
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Source('tarmac_base.cc')
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Source('tarmac_parser.cc')
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66
src/arch/arm/tracers/TarmacTrace.py
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66
src/arch/arm/tracers/TarmacTrace.py
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@@ -0,0 +1,66 @@
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# Copyright (c) 2018 ARM Limited
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# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Giacomo Gabrielli
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# Giacomo Travaglini
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from m5.SimObject import SimObject
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from m5.params import *
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from InstTracer import InstTracer
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class TarmacParser(InstTracer):
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type = 'TarmacParser'
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cxx_class = 'Trace::TarmacParser'
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cxx_header = "arch/arm/tracers/tarmac_parser.hh"
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path_to_trace = Param.String("tarmac.log", "path to TARMAC trace")
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start_pc = Param.Int(
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0x0, "tracing starts when the PC gets this value; ignored if 0x0")
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exit_on_diff = Param.Bool(False,
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"stop simulation after first mismatch is detected")
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exit_on_insn_diff = Param.Bool(False,
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"stop simulation after first mismatch on PC or opcode is detected")
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mem_wr_check = Param.Bool(False,
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"enable check of memory write accesses")
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cpu_id = Param.Bool(False,
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"true if trace format includes the CPU id")
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ignore_mem_addr = Param.AddrRange(AddrRange(0, size=0),
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"Range of unverifiable memory addresses")
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116
src/arch/arm/tracers/tarmac_base.cc
Normal file
116
src/arch/arm/tracers/tarmac_base.cc
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@@ -0,0 +1,116 @@
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/*
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* Copyright (c) 2017-2018 ARM Limited
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* All rights reserved
|
||||
*
|
||||
* The license below extends only to copyright in the software and shall
|
||||
* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
||||
* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
|
||||
* unmodified and in its entirety in all distributions of the software,
|
||||
* modified or unmodified, in source code or in binary form.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Giacomo Travaglini
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*/
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#include "arch/arm/tracers/tarmac_base.hh"
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#include <algorithm>
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#include <string>
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#include "config/the_isa.hh"
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#include "cpu/reg_class.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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using namespace TheISA;
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namespace Trace {
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TarmacBaseRecord::TarmacBaseRecord(Tick _when, ThreadContext *_thread,
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const StaticInstPtr _staticInst,
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PCState _pc,
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const StaticInstPtr _macroStaticInst)
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: InstRecord(_when, _thread, _staticInst, _pc, _macroStaticInst)
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{
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}
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TarmacBaseRecord::InstEntry::InstEntry(
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ThreadContext* thread,
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PCState pc,
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const StaticInstPtr staticInst,
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bool predicate)
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: taken(predicate) ,
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addr(pc.instAddr()) ,
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opcode(staticInst->machInst & 0xffffffff),
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disassemble(staticInst->disassemble(addr)),
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isetstate(pcToISetState(pc)),
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mode(MODE_USER)
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{
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// Operating mode gained by reading the architectural register (CPSR)
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const CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
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mode = (OperatingMode) (uint8_t)cpsr.mode;
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// In Tarmac, instruction names are printed in capital
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// letters.
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std::for_each(disassemble.begin(), disassemble.end(),
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[](char& c) { c = toupper(c); });
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}
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TarmacBaseRecord::RegEntry::RegEntry(PCState pc)
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: isetstate(pcToISetState(pc))
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{
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}
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TarmacBaseRecord::MemEntry::MemEntry (
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uint8_t _size,
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Addr _addr,
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uint64_t _data)
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: size(_size), addr(_addr), data(_data)
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{
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}
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TarmacBaseRecord::ISetState
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TarmacBaseRecord::pcToISetState(PCState pc)
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{
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TarmacBaseRecord::ISetState isetstate;
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if (pc.aarch64())
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isetstate = TarmacBaseRecord::ISET_A64;
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else if (!pc.thumb() && !pc.jazelle())
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isetstate = TarmacBaseRecord::ISET_ARM;
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else if (pc.thumb() && !pc.jazelle())
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isetstate = TarmacBaseRecord::ISET_THUMB;
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else
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// No Jazelle state in TARMAC
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isetstate = TarmacBaseRecord::ISET_UNSUPPORTED;
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return isetstate;
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}
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} // namespace Trace
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144
src/arch/arm/tracers/tarmac_base.hh
Normal file
144
src/arch/arm/tracers/tarmac_base.hh
Normal file
@@ -0,0 +1,144 @@
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/*
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* Copyright (c) 2011,2017-2018 ARM Limited
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* All rights reserved
|
||||
*
|
||||
* The license below extends only to copyright in the software and shall
|
||||
* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
||||
* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
|
||||
* unmodified and in its entirety in all distributions of the software,
|
||||
* modified or unmodified, in source code or in binary form.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Giacomo Gabrielli
|
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* Giacomo Travaglini
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*/
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/**
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* @file: This file contains the data structure used to rappresent
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* Tarmac entities/informations. These data structures will
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* be used and extended by either the Tarmac Parser and
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* the Tarmac Tracer.
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* Instruction execution is matched by Records, so that for
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* every instruction executed there is a corresponding record.
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* A trace is made of Records (Generated or Parsed) and a record
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* is made of Entries.
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*/
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#ifndef __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
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#define __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
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#include "arch/arm/registers.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/static_inst.hh"
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#include "sim/insttracer.hh"
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class ThreadContext;
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namespace Trace {
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class TarmacBaseRecord : public InstRecord
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{
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public:
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/** TARMAC trace record type. */
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enum TarmacRecordType {
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TARMAC_INST,
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TARMAC_REG,
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TARMAC_MEM,
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TARMAC_UNSUPPORTED,
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};
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/** ARM instruction set state. */
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enum ISetState { ISET_ARM, ISET_THUMB, ISET_A64,
|
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ISET_UNSUPPORTED };
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/** ARM register type. */
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enum RegType { REG_R, REG_X, REG_S, REG_D, REG_Q, REG_MISC };
|
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/** TARMAC instruction trace record. */
|
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struct InstEntry
|
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{
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InstEntry() = default;
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InstEntry(ThreadContext* thread,
|
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TheISA::PCState pc,
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const StaticInstPtr staticInst,
|
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bool predicate);
|
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|
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bool taken;
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Addr addr;
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ArmISA::MachInst opcode;
|
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std::string disassemble;
|
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ISetState isetstate;
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ArmISA::OperatingMode mode;
|
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};
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|
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/** TARMAC register trace record. */
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struct RegEntry
|
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{
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RegEntry() = default;
|
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RegEntry(TheISA::PCState pc);
|
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|
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RegType type;
|
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RegIndex index;
|
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ISetState isetstate;
|
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uint64_t valueHi;
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uint64_t valueLo;
|
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};
|
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|
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/** TARMAC memory access trace record (stores only). */
|
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struct MemEntry
|
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{
|
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MemEntry() = default;
|
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MemEntry(uint8_t _size, Addr _addr, uint64_t _data);
|
||||
|
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uint8_t size;
|
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Addr addr;
|
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uint64_t data;
|
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};
|
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|
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public:
|
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TarmacBaseRecord(Tick _when, ThreadContext *_thread,
|
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const StaticInstPtr _staticInst, TheISA::PCState _pc,
|
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const StaticInstPtr _macroStaticInst = NULL);
|
||||
|
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virtual void dump() = 0;
|
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|
||||
/**
|
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* Returns the Instruction Set State according to the current
|
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* PCState.
|
||||
*
|
||||
* @param pc program counter (PCState) variable
|
||||
* @return Instruction Set State for the given PCState
|
||||
*/
|
||||
static ISetState pcToISetState(TheISA::PCState pc);
|
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};
|
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|
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|
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} // namespace Trace
|
||||
|
||||
#endif // __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
|
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1136
src/arch/arm/tracers/tarmac_parser.cc
Normal file
1136
src/arch/arm/tracers/tarmac_parser.cc
Normal file
File diff suppressed because it is too large
Load Diff
299
src/arch/arm/tracers/tarmac_parser.hh
Normal file
299
src/arch/arm/tracers/tarmac_parser.hh
Normal file
@@ -0,0 +1,299 @@
|
||||
/*
|
||||
* Copyright (c) 2011,2017-2018 ARM Limited
|
||||
* All rights reserved
|
||||
*
|
||||
* The license below extends only to copyright in the software and shall
|
||||
* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
||||
* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
|
||||
* unmodified and in its entirety in all distributions of the software,
|
||||
* modified or unmodified, in source code or in binary form.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Giacomo Gabrielli
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file This module implements a bridge between TARMAC traces, as generated by
|
||||
* other models, and gem5 (AtomicCPU model). Its goal is to detect possible
|
||||
* inconsistencies between the two models as soon as they occur. The module
|
||||
* takes a TARMAC trace as input, which is used to compare the architectural
|
||||
* state of the two models after each simulated instruction.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
|
||||
#define __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
|
||||
|
||||
#include <fstream>
|
||||
#include <unordered_map>
|
||||
|
||||
#include "arch/arm/registers.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "base/types.hh"
|
||||
#include "cpu/static_inst.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "mem/request.hh"
|
||||
#include "params/TarmacParser.hh"
|
||||
#include "sim/insttracer.hh"
|
||||
#include "tarmac_base.hh"
|
||||
|
||||
namespace Trace {
|
||||
|
||||
class TarmacParserRecord : public TarmacBaseRecord
|
||||
{
|
||||
public:
|
||||
/**
|
||||
* Event triggered to check the value of the destination registers. Needed
|
||||
* to handle some cases where registers are modified after the trace record
|
||||
* has been dumped. E.g., the SVC instruction updates the CPSR and SPSR as
|
||||
* part of the fault handling routine.
|
||||
*/
|
||||
struct TarmacParserRecordEvent: public Event
|
||||
{
|
||||
/**
|
||||
* Reference to the TARMAC trace object to which this record belongs.
|
||||
*/
|
||||
TarmacParser& parent;
|
||||
/** Current thread context. */
|
||||
ThreadContext* thread;
|
||||
/** Current instruction. */
|
||||
const StaticInstPtr inst;
|
||||
/** PC of the current instruction. */
|
||||
TheISA::PCState pc;
|
||||
/** True if a mismatch has been detected for this instruction. */
|
||||
bool mismatch;
|
||||
/**
|
||||
* True if a mismatch has been detected for this instruction on PC or
|
||||
* opcode.
|
||||
*/
|
||||
bool mismatchOnPcOrOpcode;
|
||||
|
||||
TarmacParserRecordEvent(TarmacParser& _parent,
|
||||
ThreadContext *_thread,
|
||||
const StaticInstPtr _inst,
|
||||
TheISA::PCState _pc,
|
||||
bool _mismatch,
|
||||
bool _mismatch_on_pc_or_opcode) :
|
||||
parent(_parent), thread(_thread), inst(_inst), pc(_pc),
|
||||
mismatch(_mismatch),
|
||||
mismatchOnPcOrOpcode(_mismatch_on_pc_or_opcode)
|
||||
{
|
||||
}
|
||||
|
||||
void process();
|
||||
const char *description() const;
|
||||
};
|
||||
|
||||
struct ParserInstEntry : public InstEntry
|
||||
{
|
||||
public:
|
||||
uint64_t seq_num;
|
||||
};
|
||||
|
||||
struct ParserRegEntry : public RegEntry
|
||||
{
|
||||
public:
|
||||
char repr[16];
|
||||
};
|
||||
|
||||
struct ParserMemEntry : public MemEntry
|
||||
{ };
|
||||
|
||||
static const int MaxLineLength = 256;
|
||||
|
||||
/**
|
||||
* Print a mismatch header containing the instruction fields as reported
|
||||
* by gem5.
|
||||
*/
|
||||
static void printMismatchHeader(const StaticInstPtr inst,
|
||||
TheISA::PCState pc);
|
||||
|
||||
TarmacParserRecord(Tick _when, ThreadContext *_thread,
|
||||
const StaticInstPtr _staticInst, TheISA::PCState _pc,
|
||||
TarmacParser& _parent,
|
||||
const StaticInstPtr _macroStaticInst = NULL);
|
||||
|
||||
void dump() override;
|
||||
|
||||
/**
|
||||
* Performs a memory access to read the value written by a previous write.
|
||||
* @return False if the result of the memory access should be ignored
|
||||
* (faulty memory access, etc.).
|
||||
*/
|
||||
bool readMemNoEffect(Addr addr, uint8_t *data, unsigned size,
|
||||
unsigned flags);
|
||||
|
||||
private:
|
||||
/**
|
||||
* Advances the TARMAC trace up to the next instruction,
|
||||
* register, or memory access record. The collected data is stored
|
||||
* in one of {inst/reg/mem}_record.
|
||||
* @return False if EOF is reached.
|
||||
*/
|
||||
bool advanceTrace();
|
||||
|
||||
/** Returns the string representation of an instruction set state. */
|
||||
const char *iSetStateToStr(ISetState isetstate) const;
|
||||
|
||||
/** Buffer for instruction trace records. */
|
||||
static ParserInstEntry instRecord;
|
||||
|
||||
/** Buffer for register trace records. */
|
||||
static ParserRegEntry regRecord;
|
||||
|
||||
/** Buffer for memory access trace records (stores only). */
|
||||
static ParserMemEntry memRecord;
|
||||
|
||||
/** Type of last parsed record. */
|
||||
static TarmacRecordType currRecordType;
|
||||
|
||||
/** Buffer used for trace file parsing. */
|
||||
static char buf[MaxLineLength];
|
||||
|
||||
/** List of records of destination registers. */
|
||||
static std::list<ParserRegEntry> destRegRecords;
|
||||
|
||||
/** Map from misc. register names to indexes. */
|
||||
using MiscRegMap = std::unordered_map<std::string, RegIndex>;
|
||||
static MiscRegMap miscRegMap;
|
||||
|
||||
/**
|
||||
* True if a TARMAC instruction record has already been parsed for this
|
||||
* instruction.
|
||||
*/
|
||||
bool parsingStarted;
|
||||
|
||||
/** True if a mismatch has been detected for this instruction. */
|
||||
bool mismatch;
|
||||
|
||||
/**
|
||||
* True if a mismatch has been detected for this instruction on PC or
|
||||
* opcode.
|
||||
*/
|
||||
bool mismatchOnPcOrOpcode;
|
||||
|
||||
/** Request for memory write checks. */
|
||||
Request memReq;
|
||||
|
||||
protected:
|
||||
TarmacParser& parent;
|
||||
};
|
||||
|
||||
/**
|
||||
* Tarmac Parser: this tracer parses an existing Tarmac trace and it
|
||||
* diffs it with gem5 simulation status, comparing results and
|
||||
* reporting architectural mismatches if any.
|
||||
*/
|
||||
class TarmacParser : public InstTracer
|
||||
{
|
||||
friend class TarmacParserRecord;
|
||||
|
||||
public:
|
||||
typedef TarmacParserParams Params;
|
||||
|
||||
TarmacParser(const Params *p) : InstTracer(p), startPc(p->start_pc),
|
||||
exitOnDiff(p->exit_on_diff),
|
||||
exitOnInsnDiff(p->exit_on_insn_diff),
|
||||
memWrCheck(p->mem_wr_check),
|
||||
ignoredAddrRange(p->ignore_mem_addr),
|
||||
cpuId(p->cpu_id),
|
||||
macroopInProgress(false)
|
||||
{
|
||||
assert(!(exitOnDiff && exitOnInsnDiff));
|
||||
|
||||
trace.open(p->path_to_trace.c_str());
|
||||
if (startPc == 0x0) {
|
||||
started = true;
|
||||
} else {
|
||||
advanceTraceToStartPc();
|
||||
started = false;
|
||||
}
|
||||
}
|
||||
|
||||
virtual ~TarmacParser()
|
||||
{
|
||||
trace.close();
|
||||
}
|
||||
|
||||
InstRecord *
|
||||
getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
|
||||
TheISA::PCState pc,
|
||||
const StaticInstPtr macroStaticInst = NULL)
|
||||
{
|
||||
if (!started && pc.pc() == startPc)
|
||||
started = true;
|
||||
|
||||
if (started)
|
||||
return new TarmacParserRecord(when, tc, staticInst, pc, *this,
|
||||
macroStaticInst);
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
private:
|
||||
/** Helper function to advance the trace up to startPc. */
|
||||
void advanceTraceToStartPc();
|
||||
|
||||
/** TARMAC trace file. */
|
||||
std::ifstream trace;
|
||||
|
||||
/**
|
||||
* Tracing starts when the PC gets this value for the first time (ignored
|
||||
* if 0x0).
|
||||
*/
|
||||
Addr startPc;
|
||||
|
||||
/**
|
||||
* If true, the simulation is stopped as the first mismatch is detected.
|
||||
*/
|
||||
bool exitOnDiff;
|
||||
|
||||
/**
|
||||
* If true, the simulation is stopped as the first mismatch is detected on
|
||||
* PC or opcode.
|
||||
*/
|
||||
bool exitOnInsnDiff;
|
||||
|
||||
/** If true, memory write accesses are checked. */
|
||||
bool memWrCheck;
|
||||
|
||||
/** Ignored addresses (ignored if empty). */
|
||||
AddrRange ignoredAddrRange;
|
||||
|
||||
/** If true, the trace format includes the CPU id. */
|
||||
bool cpuId;
|
||||
|
||||
/** True if tracing has started. */
|
||||
bool started;
|
||||
|
||||
/** True if a macroop is currently in progress. */
|
||||
bool macroopInProgress;
|
||||
};
|
||||
|
||||
} // namespace Trace
|
||||
|
||||
#endif // __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
|
||||
Reference in New Issue
Block a user