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arch-arm: Add AArch32 SVC Semihosting interface

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AArch32 Svc instruction is now able to issue Arm Semihosting commands as
the AArch64 counterpart in either Arm and Thumb mode.

Change-Id: Ibe47ac23d0c26f3f819cc0e2b3ee874b5cdbb3d3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8371
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-02-13 13:55:36 +00:00
parent a7083ece99
commit 26b03914d7
1 changed files with 15 additions and 4 deletions
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19
src/arch/arm/isa/insts/misc.isa
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@@ -40,15 +40,26 @@
let {{
svcCode = '''
fault = std::make_shared<SupervisorCall>(machInst, imm);
ThreadContext *tc = xc->tcBase();
const auto semihost_imm = Thumb? 0xAB : 0x123456;
if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
R0 = ArmSystem::callSemihosting32(tc, R0, R1);
} else {
fault = std::make_shared<SupervisorCall>(machInst, imm);
}
'''
svcIop = InstObjParams("svc", "Svc", "ImmOp",
{ "code": svcCode,
"predicate_test": predicateTest },
["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
"predicate_test": predicateTest,
"thumb_semihost": '0xAB',
"arm_semihost": '0x123456' },
["IsSyscall", "IsNonSpeculative",
"IsSerializeAfter"])
header_output = ImmOpDeclare.subst(svcIop)
decoder_output = ImmOpConstructor.subst(svcIop)
decoder_output = SemihostConstructor.subst(svcIop)
exec_output = PredOpExecute.subst(svcIop)
smcCode = '''