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SE/FS: Get rid of FULL_SYSTEM in MIPS.

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This commit is contained in:
Gabe Black
2011-10-30 18:39:38 -07:00
parent 8009b53c41
commit 248033f31e
15 changed files with 45 additions and 163 deletions
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11
src/arch/mips/BISystem.py
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@@ -32,10 +32,9 @@ from m5.defines import buildEnv
from System import *
if buildEnv['FULL_SYSTEM']:
class BareIronMipsSystem(MipsSystem):
type = 'BareIronMipsSystem'
system_type = 34
system_rev = 1 << 10
hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
class BareIronMipsSystem(MipsSystem):
type = 'BareIronMipsSystem'
system_type = 34
system_rev = 1 << 10
hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")

25
src/arch/mips/MipsSystem.py
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@@ -43,19 +43,18 @@ class MipsSystem(System):
system_rev = Param.UInt64("Revision of system we are emulating")
load_addr_mask = 0xffffffffff
if buildEnv['FULL_SYSTEM']:
class LinuxMipsSystem(MipsSystem):
type = 'LinuxMipsSystem'
system_type = 34
system_rev = 1 << 10
class LinuxMipsSystem(MipsSystem):
type = 'LinuxMipsSystem'
system_type = 34
system_rev = 1 << 10
boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
"boot processor frequency")
boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
"boot processor frequency")
class BareIronMipsSystem(MipsSystem):
type = 'BareIronMipsSystem'
bare_iron = True
system_type = 34
system_rev = 1 << 10
hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
class BareIronMipsSystem(MipsSystem):
type = 'BareIronMipsSystem'
bare_iron = True
system_type = 34
system_rev = 1 << 10
hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")

23
src/arch/mips/SConscript
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@@ -33,32 +33,29 @@
Import('*')
if env['TARGET_ISA'] == 'mips':
Source('bare_iron/system.cc')
Source('dsp.cc')
Source('faults.cc')
Source('idle_event.cc')
Source('interrupts.cc')
Source('isa.cc')
Source('linux/linux.cc')
Source('linux/process.cc')
Source('linux/system.cc')
Source('pagetable.cc')
Source('process.cc')
Source('remote_gdb.cc')
Source('stacktrace.cc')
Source('system.cc')
Source('tlb.cc')
Source('utility.cc')
Source('vtophys.cc')
SimObject('MipsInterrupts.py')
DebugFlag('MipsPRA')
SimObject('MipsSystem.py')
SimObject('MipsTLB.py')
if env['FULL_SYSTEM']:
SimObject('MipsSystem.py')
Source('idle_event.cc')
Source('mips_core_specific.cc')
Source('system.cc')
Source('stacktrace.cc')
Source('linux/system.cc')
Source('bare_iron/system.cc')
else:
Source('process.cc')
Source('linux/linux.cc')
Source('linux/process.cc')
DebugFlag('MipsPRA')
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')

3
src/arch/mips/faults.cc
View File

@@ -37,11 +37,8 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#if !FULL_SYSTEM
#include "mem/page_table.hh"
#include "sim/process.hh"
#endif
namespace MipsISA
{

1
src/arch/mips/isa_traits.hh
View File

@@ -34,7 +34,6 @@
#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
#define __ARCH_MIPS_ISA_TRAITS_HH__
#include "arch/mips/mips_core_specific.hh"
#include "arch/mips/types.hh"
#include "base/types.hh"
#include "config/full_system.hh"

7
src/arch/mips/linux/system.cc
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@@ -47,6 +47,7 @@
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Thread.hh"
#include "dev/platform.hh"
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"
@@ -76,7 +77,7 @@ LinuxMipsSystem::LinuxMipsSystem(Params *p)
* Since we aren't using a bootloader, we have to copy the
* kernel arguments directly into the kernel's memory.
*/
virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
virtPort->writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
params()->boot_osflags.length()+1);
/**
@@ -85,7 +86,7 @@ LinuxMipsSystem::LinuxMipsSystem(Params *p)
* calculated it by using the PIT, RTC, etc.
*/
if (kernelSymtab->findAddress("est_cycle_freq", addr))
virtPort.write(addr, (uint64_t)(SimClock::Frequency /
virtPort->write(addr, (uint64_t)(SimClock::Frequency /
p->boot_cpu_frequency));
/**
@@ -95,7 +96,7 @@ LinuxMipsSystem::LinuxMipsSystem(Params *p)
* 255 ASNs.
*/
if (kernelSymtab->findAddress("dp264_mv", addr))
virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
virtPort->write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
else
panic("could not find dp264_mv\n");

46
src/arch/mips/mips_core_specific.cc
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@@ -1,46 +0,0 @@
/*
* Copyright (c) 2002, 2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Steve Reinhardt
*/
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////
//
// Machine dependent functions
//
void
MipsISA::initCPU(ThreadContext *tc, int cpuId)
{}
#endif // FULL_SYSTEM || BARE_IRON

42
src/arch/mips/mips_core_specific.hh
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@@ -1,42 +0,0 @@
/*
* Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Jaidev Patwardhan
*/
#ifndef __ARCH_MIPS_CORE_SPECIFIC_HH__
#define __ARCH_MIPS_CORE_SPECIFIC_HH__
#include "arch/mips/isa_traits.hh"
class ThreadContext;
namespace MipsISA {
void initCPU(ThreadContext *tc, int cpuId);
};
#endif // __ARCH_MIPS_CORE_SPECIFIC_HH__

10
src/arch/mips/remote_gdb.cc
View File

@@ -137,12 +137,12 @@
#include "arch/mips/remote_gdb.hh"
#include "arch/mips/vtophys.hh"
#include "config/full_system.hh"
#include "cpu/decode.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
#include "mem/page_table.hh"
#include "sim/full_system.hh"
using namespace std;
using namespace MipsISA;
@@ -158,13 +158,13 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
bool
RemoteGDB::acc(Addr va, size_t len)
{
#if FULL_SYSTEM
panic("acc not implemented for MIPS FS!");
#endif
TlbEntry entry;
//Check to make sure the first byte is mapped into the processes address
//space.
return context->getProcessPtr()->pTable->lookup(va, entry);
if (FullSystem)
panic("acc not implemented for MIPS FS!");
else
return context->getProcessPtr()->pTable->lookup(va, entry);
}
/*

1
src/arch/mips/stacktrace.cc
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@@ -37,6 +37,7 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/vport.hh"
#include "sim/system.hh"
using namespace std;

7
src/arch/mips/system.cc
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@@ -38,6 +38,7 @@
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "mem/physical.hh"
#include "mem/vport.hh"
#include "params/MipsSystem.hh"
#include "sim/byteswap.hh"
@@ -45,8 +46,6 @@ using namespace LittleEndianGuest;
MipsSystem::MipsSystem(Params *p) : System(p)
{
#if FULL_SYSTEM
if (p->bare_iron == true) {
hexFile = new HexFile(params()->hex_file_name);
if (!hexFile->loadSections(functionalPort))
@@ -108,14 +107,12 @@ MipsSystem::MipsSystem(Params *p) : System(p)
} else {
panic("could not find hwrpb\n");
}
#endif
}
MipsSystem::~MipsSystem()
{
}
#if FULL_SYSTEM
Addr
MipsSystem::fixFuncEventAddr(Addr addr)
{
@@ -126,8 +123,6 @@ void
MipsSystem::setMipsAccess(Addr access)
{}
#endif
bool
MipsSystem::breakpoint()
{

7
src/arch/mips/system.hh
View File

@@ -66,7 +66,6 @@ class MipsSystem : public System
*/
void setMipsAccess(Addr access);
#if FULL_SYSTEM
/** console symbol table */
SymbolTable *consoleSymtab;
@@ -75,7 +74,6 @@ class MipsSystem : public System
/** Used by some Bare Iron Configurations */
HexFile *hexFile;
#endif
#ifndef NDEBUG
/** Event to halt the simulator if the console calls panic() */
@@ -85,9 +83,7 @@ class MipsSystem : public System
protected:
const Params *params() const { return (const Params *)_params; }
#if FULL_SYSTEM
/** Add a function-based event to the console code. */
/** Add a function-based event to the console code. */
template <class T>
T *
addConsoleFuncEvent(const char *lbl)
@@ -96,7 +92,6 @@ class MipsSystem : public System
}
virtual Addr fixFuncEventAddr(Addr addr);
#endif
};

23
src/arch/mips/utility.cc
View File

@@ -39,11 +39,9 @@
#include "cpu/thread_context.hh"
#include "sim/serialize.hh"
#if FULL_SYSTEM
#include "arch/mips/registers.hh"
#include "arch/mips/vtophys.hh"
#include "mem/vport.hh"
#endif
using namespace MipsISA;
@@ -54,23 +52,8 @@ namespace MipsISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
#if FULL_SYSTEM
if (number < 4) {
if (fp)
return tc->readFloatRegBits(FirstArgumentReg + number);
else
return tc->readIntReg(FirstArgumentReg + number);
} else {
Addr sp = tc->readIntReg(StackPointerReg);
VirtualPort *vp = tc->getVirtPort();
uint64_t arg = vp->read<uint64_t>(sp +
(number - 4) * sizeof(uint64_t));
return arg;
}
#else
panic("getArgument() is Full system only\n");
panic("getArgument() not implemented\n");
M5_DUMMY_RETURN
#endif
}
uint64_t
@@ -253,6 +236,10 @@ startupCPU(ThreadContext *tc, int cpuId)
tc->activate(0/*tc->threadId()*/);
}
void
initCPU(ThreadContext *tc, int cpuId)
{}
void
copyRegs(ThreadContext *src, ThreadContext *dest)
{

1
src/arch/mips/utility.hh
View File

@@ -108,6 +108,7 @@ RoundPage(Addr addr)
// CPU Utility
//
void startupCPU(ThreadContext *tc, int cpuId);
void initCPU(ThreadContext *tc, int cpuId);
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);

1
src/dev/mips/malta_cchip.cc
View File

@@ -37,7 +37,6 @@
#include <string>
#include <vector>
#include "arch/mips/mips_core_specific.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/intr_control.hh"