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traceflag stuff

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src/base/traceflags.py:
    add BaseCPU flag, O3CPUAll flag grouping
src/cpu/base.cc:
    Use BaseCPU flag instead of FullCPU flag

--HG--
extra : convert_revision : 32f737a2f58eb936634799f1f809e07cbba90179
This commit is contained in:
Korey Sewell
2006-07-01 19:02:43 -04:00
parent 62961a2916
commit 23cfd9489b
2 changed files with 4 additions and 3 deletions
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3
src/base/traceflags.py
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@@ -115,6 +115,7 @@ baseFlags = [
'MSHR',
'Mbox',
'MemDepUnit',
'BaseCPU'
'O3CPU',
'OzoneCPU',
'FE',
@@ -176,7 +177,7 @@ compoundFlagMap = {
'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ],
'FullCPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU', 'Activity','Scoreboard','Writeback'],
'O3CPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'O3CPU', 'Activity','Scoreboard','Writeback'],
'OzoneCPUAll' : [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU']
}

4
src/cpu/base.cc
View File

@@ -68,12 +68,12 @@ BaseCPU::BaseCPU(Params *p)
number_of_threads(p->numberOfThreads), system(p->system)
#endif
{
DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
DPRINTF(BaseCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
// add self to global list of CPUs
cpuList.push_back(this);
DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n",
DPRINTF(BaseCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n",
this);
if (number_of_threads > maxThreadsPerCPU)