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arch: cpu: Stop passing around misc registers by reference.

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These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.

Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Gabe Black
2018-10-18 17:34:08 -07:00
parent 774770a641
commit 230b892fa3
23 changed files with 58 additions and 68 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/cpu/checker/cpu.hh
View File

@@ -417,7 +417,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void
setMiscRegNoEffect(int misc_reg, const RegVal &val)
setMiscRegNoEffect(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n",
misc_reg);
@@ -426,7 +426,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void
setMiscReg(int misc_reg, const RegVal &val) override
setMiscReg(int misc_reg, RegVal val) override
{
DPRINTF(Checker, "Setting misc reg %d with effect to check later\n",
misc_reg);
@@ -443,8 +443,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void
setMiscRegOperand(const StaticInst *si, int idx,
const RegVal &val) override
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());

4
src/cpu/checker/thread_context.hh
View File

@@ -348,7 +348,7 @@ class CheckerThreadContext : public ThreadContext
{ return actualTC->readMiscReg(misc_reg); }
void
setMiscRegNoEffect(int misc_reg, const RegVal &val)
setMiscRegNoEffect(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
" and O3..\n", misc_reg);
@@ -357,7 +357,7 @@ class CheckerThreadContext : public ThreadContext
}
void
setMiscReg(int misc_reg, const RegVal &val)
setMiscReg(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
" and O3..\n", misc_reg);

4
src/cpu/exec_context.hh
View File

@@ -182,7 +182,7 @@ class ExecContext {
*/
virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
virtual void setMiscRegOperand(const StaticInst *si,
int idx, const RegVal &val) = 0;
int idx, RegVal val) = 0;
/**
* Reads a miscellaneous register, handling any architectural
@@ -194,7 +194,7 @@ class ExecContext {
* Sets a miscellaneous register, handling any architectural
* side effects due to writing that register.
*/
virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
virtual void setMiscReg(int misc_reg, RegVal val) = 0;
/** @} */

7
src/cpu/minor/exec_context.hh
View File

@@ -309,7 +309,7 @@ class ExecContext : public ::ExecContext
}
void
setMiscReg(int misc_reg, const RegVal &val) override
setMiscReg(int misc_reg, RegVal val) override
{
thread.setMiscReg(misc_reg, val);
}
@@ -323,8 +323,7 @@ class ExecContext : public ::ExecContext
}
void
setMiscRegOperand(const StaticInst *si, int idx,
const RegVal &val) override
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
@@ -431,7 +430,7 @@ class ExecContext : public ::ExecContext
}
void
setRegOtherThread(const RegId &reg, const RegVal &val,
setRegOtherThread(const RegId &reg, RegVal val,
ThreadID tid=InvalidThreadID)
{
SimpleThread *other_thread = (tid == InvalidThreadID

6
src/cpu/o3/cpu.cc
View File

@@ -1260,16 +1260,14 @@ FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
template <class Impl>
void
FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
const RegVal &val, ThreadID tid)
FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
{
this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
}
template <class Impl>
void
FullO3CPU<Impl>::setMiscReg(int misc_reg,
const RegVal &val, ThreadID tid)
FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
{
miscRegfileWrites++;
this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));

4
src/cpu/o3/cpu.hh
View File

@@ -390,12 +390,12 @@ class FullO3CPU : public BaseO3CPU
RegVal readMiscReg(int misc_reg, ThreadID tid);
/** Sets a miscellaneous register. */
void setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid);
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
void setMiscReg(int misc_reg, const RegVal &val, ThreadID tid);
void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
RegVal readIntReg(PhysRegIdPtr phys_reg);

4
src/cpu/o3/dyn_inst.hh
View File

@@ -146,7 +146,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
* might have as defined by the architecture.
*/
void
setMiscReg(int misc_reg, const RegVal &val)
setMiscReg(int misc_reg, RegVal val)
{
/** Writes to misc. registers are recorded and deferred until the
* commit stage, when updateMiscRegs() is called. First, check if
@@ -182,7 +182,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
* might have as defined by the architecture.
*/
void
setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val)
setMiscRegOperand(const StaticInst *si, int idx, RegVal val)
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());

4
src/cpu/o3/thread_context.hh
View File

@@ -331,11 +331,11 @@ class O3ThreadContext : public ThreadContext
{ return cpu->readMiscReg(misc_reg, thread->threadId()); }
/** Sets a misc. register. */
virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val);
virtual void setMiscRegNoEffect(int misc_reg, RegVal val);
/** Sets a misc. register, including any side-effects the
* write might have as defined by the architecture. */
virtual void setMiscReg(int misc_reg, const RegVal &val);
virtual void setMiscReg(int misc_reg, RegVal val);
virtual RegId flattenRegId(const RegId& regId) const;

4
src/cpu/o3/thread_context_impl.hh
View File

@@ -307,7 +307,7 @@ O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
template <class Impl>
void
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val)
{
cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
@@ -317,7 +317,7 @@ O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
template <class Impl>
void
O3ThreadContext<Impl>::setMiscReg(int misc_reg, const RegVal &val)
O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val)
{
cpu->setMiscReg(misc_reg, val, thread->threadId());

5
src/cpu/simple/exec_context.hh
View File

@@ -361,8 +361,7 @@ class SimpleExecContext : public ExecContext {
}
void
setMiscRegOperand(const StaticInst *si, int idx,
const RegVal &val) override
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
numIntRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -386,7 +385,7 @@ class SimpleExecContext : public ExecContext {
* side effects due to writing that register.
*/
void
setMiscReg(int misc_reg, const RegVal &val) override
setMiscReg(int misc_reg, RegVal val) override
{
numIntRegWrites++;
thread->setMiscReg(misc_reg, val);

4
src/cpu/simple_thread.hh
View File

@@ -489,13 +489,13 @@ class SimpleThread : public ThreadState
}
void
setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0)
setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0)
{
return isa->setMiscRegNoEffect(misc_reg, val);
}
void
setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0)
setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0)
{
return isa->setMiscReg(misc_reg, val, tc);
}

10
src/cpu/thread_context.hh
View File

@@ -278,9 +278,9 @@ class ThreadContext
virtual RegVal readMiscReg(int misc_reg) = 0;
virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val) = 0;
virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0;
virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
virtual void setMiscReg(int misc_reg, RegVal val) = 0;
virtual RegId flattenRegId(const RegId& regId) const = 0;
@@ -291,7 +291,7 @@ class ThreadContext
}
virtual void
setRegOtherThread(const RegId& misc_reg, const RegVal &val, ThreadID tid)
setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
{
}
@@ -541,10 +541,10 @@ class ProxyThreadContext : public ThreadContext
RegVal readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }
void setMiscRegNoEffect(int misc_reg, const RegVal &val)
void setMiscRegNoEffect(int misc_reg, RegVal val)
{ return actualTC->setMiscRegNoEffect(misc_reg, val); }
void setMiscReg(int misc_reg, const RegVal &val)
void setMiscReg(int misc_reg, RegVal val)
{ return actualTC->setMiscReg(misc_reg, val); }
RegId flattenRegId(const RegId& regId) const