More progress toward actually running a program.

See configs/test.py for test config (using simple
binary in my home directory on zizzer).

base/chunk_generator.hh:
    Fix assertion for chunkSize == 0 (not a power of 2)
base/intmath.hh:
    Fix roundDown to take integer alignments.
cpu/base.cc:
    Register exec contexts regardless of state (not sure why
    this check was in here in the first place).
mem/physical.cc:
    Add breaks to switch.
python/m5/objects/BaseCPU.py:
    Default mem to Parent.any (e.g. get from System).
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
    HierParams is gone.
python/m5/objects/PhysicalMemory.py:
    mmu param is full-system only.
sim/process.cc:
    Stack mapping request must be page-aligned and page-sized.
    Don't delete objFile object in create since we are counting
    on it being around for startup().

--HG--
extra : convert_revision : 90c43ee927e7d82a045d6e10302d965797d006f7

base/chunk_generator.hh

@@ -77,7 +77,7 @@ class ChunkGenerator
         : chunkSize(_chunkSize)
     {
         // chunkSize must be a power of two
-        assert(isPowerOf2(chunkSize));
+        assert(chunkSize == 0 || isPowerOf2(chunkSize));
 
         // set up initial chunk.
         curAddr = startAddr;

base/intmath.hh

@@ -202,9 +202,9 @@ roundUp(T val, int align)
 
 template <class T>
 inline T
-roundDown(T val, T align)
+roundDown(T val, int align)
 {
-    T mask = align - 1;
+    T mask = (T)align - 1;
     return val & ~mask;
 }
 

configs/test.py

@@ -0,0 +1,8 @@
+from m5 import *
+AddToPath('/z/stever/bk/m5-test')
+import Benchmarks
+
+mem = PhysicalMemory()
+cpu = SimpleCPU(workload=Benchmarks.HelloWorld(), mem=mem)
+system = System(physmem=mem, cpu=cpu)
+root = Root(system=system)

cpu/base.cc

@@ -212,17 +212,15 @@ BaseCPU::registerExecContexts()
     for (int i = 0; i < execContexts.size(); ++i) {
         ExecContext *xc = execContexts[i];
 
-        if (xc->status() == ExecContext::Suspended) {
 #if FULL_SYSTEM
-            int id = params->cpu_id;
-            if (id != -1)
-                id += i;
+        int id = params->cpu_id;
+        if (id != -1)
+            id += i;
 
-            xc->cpu_id = system->registerExecContext(xc, id);
+        xc->cpu_id = system->registerExecContext(xc, id);
 #else
-            xc->cpu_id = xc->process->registerExecContext(xc);
+        xc->cpu_id = xc->process->registerExecContext(xc);
 #endif
-        }
     }
 }
 

mem/physical.cc

@@ -167,8 +167,10 @@ PhysicalMemory::doFunctionalAccess(Packet &pkt)
     switch (pkt.cmd) {
       case Read:
         memcpy(pkt.data, pmem_addr + pkt.addr - base_addr, pkt.size);
+        break;
       case Write:
         memcpy(pmem_addr + pkt.addr - base_addr, pkt.data, pkt.size);
+        break;
       default:
         panic("unimplemented");
     }

python/m5/objects/BaseCPU.py

@@ -9,7 +9,7 @@ class BaseCPU(SimObject):
         system = Param.System(Parent.any, "system object")
         cpu_id = Param.Int(-1, "CPU identifier")
     else:
-        mem = Param.Memory("memory")
+        mem = Param.Memory(Parent.any, "memory")
         workload = VectorParam.Process("processes to run")
 
     max_insts_all_threads = Param.Counter(0,

python/m5/objects/Ethernet.py

@@ -69,7 +69,6 @@ class EtherDevBase(PciDevice):
 
     physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
 
-    hier = Param.HierParams(Parent.any, "Hierarchy global variables")
     payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
     dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
     dma_read_factor = Param.Latency('0us', "multiplier for dma reads")

python/m5/objects/PhysicalMemory.py

@@ -5,4 +5,5 @@ class PhysicalMemory(Memory):
     type = 'PhysicalMemory'
     range = Param.AddrRange("Device Address")
     file = Param.String('', "memory mapped file")
-    mmu = Param.MemoryController(Parent.any, "Memory Controller")
+    if build_env['FULL_SYSTEM']:
+        mmu = Param.MemoryController(Parent.any, "Memory Controller")

python/m5/objects/Root.py

@@ -1,5 +1,4 @@
 from m5 import *
-from HierParams import HierParams
 from Serialize import Serialize
 from Statistics import Statistics
 from Trace import Trace
@@ -13,12 +12,9 @@ class Root(SimObject):
         "print a progress message every n ticks (0 = never)")
     output_file = Param.String('cout', "file to dump simulator output to")
     checkpoint = Param.String('', "checkpoint file to load")
-#    hier = Param.HierParams(HierParams(do_data = False, do_events = True),
-#                            "shared memory hierarchy parameters")
 #    stats = Param.Statistics(Statistics(), "statistics object")
 #    trace = Param.Trace(Trace(), "trace object")
 #    serialize = Param.Serialize(Serialize(), "checkpoint generation options")
-    hier = HierParams(do_data = False, do_events = True)
     stats = Statistics()
     trace = Trace()
     exetrace = ExecutionTrace()

sim/process.cc

@@ -331,7 +331,8 @@ LiveProcess::startup()
     stack_min &= ~7;
     stack_size = stack_base - stack_min;
     // map memory
-    pTable->allocate(stack_min, stack_size);
+    pTable->allocate(roundDown(stack_min, VMPageSize),
+                     roundUp(stack_size, VMPageSize));
 
     // map out initial stack contents
     Addr argv_array_base = stack_min + sizeof(uint64_t); // room for argc
@@ -396,8 +397,6 @@ LiveProcess::create(const string &nm, System *system,
         fatal("Unknown object file architecture.");
     }
 
-    delete objFile;
-
     if (process == NULL)
         fatal("Unknown error creating process object.");