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configs: Port MemConfig to the common object list

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Port MemConfig to use the common object list.

Change-Id: If421c2745ac3431718a5170314045b456fc64a90
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20592
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Daniel R. Carvalho
2019-09-03 15:24:23 +02:00
committed by Daniel Carvalho
parent b2b06531b8
commit 224da08be7
10 changed files with 22 additions and 66 deletions
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54
configs/common/MemConfig.py
View File

@@ -40,59 +40,9 @@ from __future__ import print_function
from __future__ import absolute_import
import m5.objects
import inspect
import sys
from textwrap import TextWrapper
from common import ObjectList
from . import HMC
# Dictionary of mapping names of real memory controller models to
# classes.
_mem_classes = {}
def is_mem_class(cls):
"""Determine if a class is a memory controller that can be instantiated"""
# We can't use the normal inspect.isclass because the ParamFactory
# and ProxyFactory classes have a tendency to confuse it.
try:
return issubclass(cls, m5.objects.AbstractMemory) and \
not cls.abstract
except TypeError:
return False
def get(name):
"""Get a memory class from a user provided class name."""
try:
mem_class = _mem_classes[name]
return mem_class
except KeyError:
print("%s is not a valid memory controller." % (name,))
sys.exit(1)
def print_mem_list():
"""Print a list of available memory classes."""
print("Available memory classes:")
doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
for name, cls in _mem_classes.items():
print("\t%s" % name)
# Try to extract the class documentation from the class help
# string.
doc = inspect.getdoc(cls)
if doc:
for line in doc_wrapper.wrap(doc):
print(line)
def mem_names():
"""Return a list of valid memory names."""
return list(_mem_classes.keys())
# Add all memory controllers in the object hierarchy.
for name, cls in inspect.getmembers(m5.objects, is_mem_class):
_mem_classes[name] = cls
def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
"""
Helper function for creating a single memoy controller from the given
@@ -200,7 +150,7 @@ def config_mem(options, system):
if 2 ** intlv_bits != nbr_mem_ctrls:
fatal("Number of memory channels must be a power of 2")
cls = get(opt_mem_type)
cls = ObjectList.mem_list.get(opt_mem_type)
mem_ctrls = []
if opt_elastic_trace_en and not issubclass(cls, m5.objects.SimpleMemory):

1
configs/common/ObjectList.py
View File

@@ -139,6 +139,7 @@ bp_list = ObjectList(m5.objects.BranchPredictor)
cpu_list = CPUList(m5.objects.BaseCPU)
hwp_list = ObjectList(m5.objects.BasePrefetcher)
indirect_bp_list = ObjectList(m5.objects.IndirectPredictor)
mem_list = ObjectList(m5.objects.AbstractMemory)
def _subclass_tester(name):
sub_class = getattr(m5.objects, name, None)

5
configs/common/Options.py
View File

@@ -47,7 +47,6 @@ from m5.objects import *
from .Benchmarks import *
from . import ObjectList
from . import MemConfig
from . import PlatformConfig
def _listCpuTypes(option, opt, value, parser):
@@ -67,7 +66,7 @@ def _listIndirectBPTypes(option, opt, value, parser):
sys.exit(0)
def _listMemTypes(option, opt, value, parser):
MemConfig.print_mem_list()
ObjectList.mem_list.print()
sys.exit(0)
def _listPlatformTypes(option, opt, value, parser):
@@ -93,7 +92,7 @@ def addNoISAOptions(parser):
action="callback", callback=_listMemTypes,
help="List available memory types")
parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
choices=MemConfig.mem_names(),
choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
parser.add_option("--mem-channels", type="int", default=1,
help = "number of memory channels")

3
configs/common/Simulation.py
View File

@@ -48,7 +48,6 @@ from os.path import join as joinpath
from common import CpuConfig
from . import ObjectList
from . import MemConfig
import m5
from m5.defines import buildEnv
@@ -97,7 +96,7 @@ def setCPUClass(options):
def setMemClass(options):
"""Returns a memory controller class."""
return MemConfig.get(options.mem_type)
return ObjectList.mem_list.get(options.mem_type)
def setWorkCountOptions(system, options):
if options.work_item_id != None:

3
configs/dram/lat_mem_rd.py
View File

@@ -48,6 +48,7 @@ from m5.util import addToPath
from m5.stats import periodicStatDump
addToPath('../')
from common import ObjectList
from common import MemConfig
addToPath('../../util')
@@ -84,7 +85,7 @@ except:
parser = optparse.OptionParser()
parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
choices=MemConfig.mem_names(),
choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
parser.add_option("--mem-size", action="store", type="string",
default="16MB",

3
configs/dram/low_power_sweep.py
View File

@@ -48,6 +48,7 @@ from m5.stats import periodicStatDump
addToPath('../')
from common import ObjectList
from common import MemConfig
# This script aims at triggering low power state transitions in the DRAM
@@ -61,7 +62,7 @@ parser = argparse.ArgumentParser(
# Use a single-channel DDR4-2400 in 16x4 configuration by default
parser.add_argument("--mem-type", default="DDR4_2400_16x4",
choices=MemConfig.mem_names(),
choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
parser.add_argument("--mem-ranks", "-r", type=int, default=1,

3
configs/dram/sweep.py
View File

@@ -48,6 +48,7 @@ from m5.stats import periodicStatDump
addToPath('../')
from common import ObjectList
from common import MemConfig
# this script is helpful to sweep the efficiency of a specific memory
@@ -64,7 +65,7 @@ dram_generators = {
# Use a single-channel DDR3-1600 x64 (8x8 topology) by default
parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
choices=MemConfig.mem_names(),
choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
parser.add_option("--mem-ranks", "-r", type="int", default=1,

3
configs/example/arm/starter_fs.py
View File

@@ -56,6 +56,7 @@ import argparse
m5.util.addToPath('../..')
from common import SysPaths
from common import ObjectList
from common import MemConfig
from common.cores.arm import HPI
@@ -214,7 +215,7 @@ def main():
parser.add_argument("--num-cores", type=int, default=1,
help="Number of CPU cores")
parser.add_argument("--mem-type", default="DDR3_1600_8x8",
choices=MemConfig.mem_names(),
choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
parser.add_argument("--mem-channels", type=int, default=1,
help = "number of memory channels")

3
configs/example/arm/starter_se.py
View File

@@ -55,6 +55,7 @@ import shlex
m5.util.addToPath('../..')
from common import ObjectList
from common import MemConfig
from common.cores.arm import HPI
@@ -194,7 +195,7 @@ def main():
parser.add_argument("--num-cores", type=int, default=1,
help="Number of CPU cores")
parser.add_argument("--mem-type", default="DDR3_1600_8x8",
choices=MemConfig.mem_names(),
choices=ObjectList.mem_list.get_names(),
help = "type of memory to use")
parser.add_argument("--mem-channels", type=int, default=2,
help = "number of memory channels")

10
configs/ruby/Ruby.py
View File

@@ -49,6 +49,7 @@ from m5.util import addToPath, fatal
addToPath('../')
from common import ObjectList
from common import MemConfig
from common import FileSystemConfig
@@ -115,9 +116,10 @@ def setup_memory_controllers(system, ruby, dir_cntrls, options):
dir_ranges = []
for r in system.mem_ranges:
mem_ctrl = MemConfig.create_mem_ctrl(
MemConfig.get(options.mem_type), r, index, options.num_dirs,
int(math.log(options.num_dirs, 2)), intlv_size)
mem_type = ObjectList.mem_list.get(options.mem_type)
mem_ctrl = MemConfig.create_mem_ctrl(mem_type, r, index,
options.num_dirs, int(math.log(options.num_dirs, 2)),
intlv_size)
if options.access_backing_store:
mem_ctrl.kvm_map=False
@@ -131,7 +133,7 @@ def setup_memory_controllers(system, ruby, dir_cntrls, options):
mem_ctrl.port = dir_cntrl.memory
# Enable low-power DRAM states if option is set
if issubclass(MemConfig.get(options.mem_type), DRAMCtrl):
if issubclass(mem_type, DRAMCtrl):
mem_ctrl.enable_dram_powerdown = \
options.enable_dram_powerdown