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misc: Substitute pointer to Request with aliased RequestPtr

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Every usage of Request* in the code has been replaced with the
RequestPtr alias.  This is a preparing patch for when RequestPtr will be
the typdefed to a smart pointer to Request rather then a raw pointer to
Request.

Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10995
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
This commit is contained in:
Giacomo Travaglini
2018-06-03 13:10:26 +01:00
parent 59505f7305
commit 2113b21996
32 changed files with 68 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/cpu/base_dyn_inst.hh
View File

@@ -893,9 +893,9 @@ BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
Request::Flags flags)
{
instFlags[ReqMade] = true;
Request *req = NULL;
Request *sreqLow = NULL;
Request *sreqHigh = NULL;
RequestPtr req = NULL;
RequestPtr sreqLow = NULL;
RequestPtr sreqHigh = NULL;
if (instFlags[ReqMade] && translationStarted()) {
req = savedReq;
@@ -949,9 +949,9 @@ BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
traceData->setMem(addr, size, flags);
instFlags[ReqMade] = true;
Request *req = NULL;
Request *sreqLow = NULL;
Request *sreqHigh = NULL;
RequestPtr req = NULL;
RequestPtr sreqLow = NULL;
RequestPtr sreqHigh = NULL;
if (instFlags[ReqMade] && translationStarted()) {
req = savedReq;

2
src/cpu/checker/cpu.cc
View File

@@ -337,7 +337,7 @@ CheckerCPU::dbg_vtophys(Addr addr)
* Checks if the flags set by the Checker and Checkee match.
*/
bool
CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
CheckerCPU::checkFlags(RequestPtr unverified_req, Addr vAddr,
Addr pAddr, int flags)
{
Addr unverifiedVAddr = unverified_req->getVaddr();

4
src/cpu/checker/cpu.hh
View File

@@ -531,7 +531,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
dumpAndExit();
}
bool checkFlags(Request *unverified_req, Addr vAddr,
bool checkFlags(RequestPtr unverified_req, Addr vAddr,
Addr pAddr, int flags);
void dumpAndExit();
@@ -540,7 +540,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
SimpleThread *threadBase() { return thread; }
InstResult unverifiedResult;
Request *unverifiedReq;
RequestPtr unverifiedReq;
uint8_t *unverifiedMemData;
bool changedPC;

4
src/cpu/minor/lsq.cc
View File

@@ -423,7 +423,7 @@ LSQ::SplitDataRequest::makeFragmentRequests()
}
}
Request *fragment = new Request();
RequestPtr fragment = new Request();
fragment->setContext(request.contextId());
fragment->setVirt(0 /* asid */,
@@ -452,7 +452,7 @@ LSQ::SplitDataRequest::makeFragmentPackets()
for (unsigned int fragment_index = 0; fragment_index < numFragments;
fragment_index++)
{
Request *fragment = fragmentRequests[fragment_index];
RequestPtr fragment = fragmentRequests[fragment_index];
DPRINTFS(MinorMem, (&port), "Making packet %d for request: %s"
" (%d, 0x%x)\n",

2
src/cpu/minor/lsq.hh
View File

@@ -399,7 +399,7 @@ class LSQ : public Named
/** Fragment Requests corresponding to the address ranges of
* each fragment */
std::vector<Request *> fragmentRequests;
std::vector<RequestPtr> fragmentRequests;
/** Packets matching fragmentRequests to issue fragments to memory */
std::vector<Packet *> fragmentPackets;

8
src/cpu/o3/lsq_unit.hh
View File

@@ -510,11 +510,11 @@ class LSQUnit {
public:
/** Executes the load at the given index. */
Fault read(Request *req, Request *sreqLow, Request *sreqHigh,
Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
int load_idx);
/** Executes the store at the given index. */
Fault write(Request *req, Request *sreqLow, Request *sreqHigh,
Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
uint8_t *data, int store_idx);
/** Returns the index of the head load instruction. */
@@ -549,7 +549,7 @@ class LSQUnit {
template <class Impl>
Fault
LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
LSQUnit<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
int load_idx)
{
DynInstPtr load_inst = loadQueue[load_idx];
@@ -883,7 +883,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
template <class Impl>
Fault
LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
LSQUnit<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
uint8_t *data, int store_idx)
{
assert(storeQueue[store_idx].inst);

2
src/cpu/o3/lsq_unit_impl.hh
View File

@@ -831,7 +831,7 @@ LSQUnit<Impl>::writebackStores()
DynInstPtr inst = storeQueue[storeWBIdx].inst;
Request *req = storeQueue[storeWBIdx].req;
RequestPtr req = storeQueue[storeWBIdx].req;
RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;

4
src/cpu/simple/atomic.cc
View File

@@ -331,7 +331,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size,
SimpleThread* thread = t_info.thread;
// use the CPU's statically allocated read request and packet objects
Request *req = &data_read_req;
RequestPtr req = &data_read_req;
if (traceData)
traceData->setMem(addr, size, flags);
@@ -435,7 +435,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
}
// use the CPU's statically allocated write request and packet objects
Request *req = &data_write_req;
RequestPtr req = &data_write_req;
if (traceData)
traceData->setMem(addr, size, flags);

2
src/cpu/simple/base.cc
View File

@@ -468,7 +468,7 @@ BaseSimpleCPU::checkForInterrupts()
void
BaseSimpleCPU::setupFetchRequest(Request *req)
BaseSimpleCPU::setupFetchRequest(RequestPtr req)
{
SimpleExecContext &t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;

2
src/cpu/simple/base.hh
View File

@@ -129,7 +129,7 @@ class BaseSimpleCPU : public BaseCPU
void checkForInterrupts();
void setupFetchRequest(Request *req);
void setupFetchRequest(RequestPtr req);
void preExecute();
void postExecute();
void advancePC(const Fault &fault);

2
src/cpu/simple/timing.cc
View File

@@ -620,7 +620,7 @@ TimingSimpleCPU::fetch()
if (needToFetch) {
_status = BaseSimpleCPU::Running;
Request *ifetch_req = new Request();
RequestPtr ifetch_req = new Request();
ifetch_req->taskId(taskId());
ifetch_req->setContext(thread->contextId());
setupFetchRequest(ifetch_req);

2
src/cpu/testers/directedtest/InvalidateGenerator.cc
View File

@@ -60,7 +60,7 @@ InvalidateGenerator::initiate()
Packet::Command cmd;
// For simplicity, requests are assumed to be 1 byte-sized
Request *req = new Request(m_address, 1, flags, masterId);
RequestPtr req = new Request(m_address, 1, flags, masterId);
//
// Based on the current state, issue a load or a store

2
src/cpu/testers/directedtest/SeriesRequestGenerator.cc
View File

@@ -60,7 +60,7 @@ SeriesRequestGenerator::initiate()
Request::Flags flags;
// For simplicity, requests are assumed to be 1 byte-sized
Request *req = new Request(m_address, 1, flags, masterId);
RequestPtr req = new Request(m_address, 1, flags, masterId);
Packet::Command cmd;
bool do_write = (random_mt.random(0, 100) < m_percent_writes);

4
src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc
View File

@@ -129,7 +129,7 @@ GarnetSyntheticTraffic::init()
void
GarnetSyntheticTraffic::completeRequest(PacketPtr pkt)
{
Request *req = pkt->req;
RequestPtr req = pkt->req;
DPRINTF(GarnetSyntheticTraffic,
"Completed injection of %s packet for address %x\n",
@@ -279,7 +279,7 @@ GarnetSyntheticTraffic::generatePkt()
//
MemCmd::Command requestType;
Request *req = nullptr;
RequestPtr req = nullptr;
Request::Flags flags;
// Inject in specific Vnet

4
src/cpu/testers/memtest/memtest.cc
View File

@@ -136,7 +136,7 @@ MemTest::getMasterPort(const std::string &if_name, PortID idx)
void
MemTest::completeRequest(PacketPtr pkt, bool functional)
{
Request *req = pkt->req;
RequestPtr req = pkt->req;
assert(req->getSize() == 1);
// this address is no longer outstanding
@@ -246,7 +246,7 @@ MemTest::tick()
bool do_functional = (random_mt.random(0, 100) < percentFunctional) &&
!uncacheable;
Request *req = new Request(paddr, 1, flags, masterId);
RequestPtr req = new Request(paddr, 1, flags, masterId);
req->setContext(id);
outstandingAddrs.insert(paddr);

8
src/cpu/testers/rubytest/Check.cc
View File

@@ -107,7 +107,7 @@ Check::initiatePrefetch()
}
// Prefetches are assumed to be 0 sized
Request *req = new Request(m_address, 0, flags,
RequestPtr req = new Request(m_address, 0, flags,
m_tester_ptr->masterId(), curTick(), m_pc);
req->setContext(index);
@@ -146,7 +146,7 @@ Check::initiateFlush()
Request::Flags flags;
Request *req = new Request(m_address, CHECK_SIZE, flags,
RequestPtr req = new Request(m_address, CHECK_SIZE, flags,
m_tester_ptr->masterId(), curTick(), m_pc);
Packet::Command cmd;
@@ -179,7 +179,7 @@ Check::initiateAction()
Addr writeAddr(m_address + m_store_count);
// Stores are assumed to be 1 byte-sized
Request *req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(),
RequestPtr req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(),
curTick(), m_pc);
req->setContext(index);
@@ -244,7 +244,7 @@ Check::initiateCheck()
}
// Checks are sized depending on the number of bytes written
Request *req = new Request(m_address, CHECK_SIZE, flags,
RequestPtr req = new Request(m_address, CHECK_SIZE, flags,
m_tester_ptr->masterId(), curTick(), m_pc);
req->setContext(index);

2
src/cpu/testers/traffic_gen/base_gen.cc
View File

@@ -59,7 +59,7 @@ BaseGen::getPacket(Addr addr, unsigned size, const MemCmd& cmd,
Request::FlagsType flags)
{
// Create new request
Request *req = new Request(addr, size, flags, masterID);
RequestPtr req = new Request(addr, size, flags, masterID);
// Dummy PC to have PC-based prefetchers latch on; get entropy into higher
// bits
req->setPC(((Addr)masterID) << 2);