2113b21996
Every usage of Request* in the code has been replaced with the RequestPtr alias. This is a preparing patch for when RequestPtr will be the typdefed to a smart pointer to Request rather then a raw pointer to Request. Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10995 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
117 lines
4.0 KiB
C++
117 lines
4.0 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
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#include "base/random.hh"
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#include "base/trace.hh"
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#include "cpu/testers/directedtest/DirectedGenerator.hh"
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#include "cpu/testers/directedtest/RubyDirectedTester.hh"
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#include "debug/DirectedTest.hh"
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SeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
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: DirectedGenerator(p),
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m_addr_increment_size(p->addr_increment_size),
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m_percent_writes(p->percent_writes)
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{
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m_status = SeriesRequestGeneratorStatus_Thinking;
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m_active_node = 0;
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m_address = 0x0;
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}
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SeriesRequestGenerator::~SeriesRequestGenerator()
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{
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}
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bool
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SeriesRequestGenerator::initiate()
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{
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DPRINTF(DirectedTest, "initiating request\n");
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assert(m_status == SeriesRequestGeneratorStatus_Thinking);
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MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
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Request::Flags flags;
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// For simplicity, requests are assumed to be 1 byte-sized
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RequestPtr req = new Request(m_address, 1, flags, masterId);
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Packet::Command cmd;
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bool do_write = (random_mt.random(0, 100) < m_percent_writes);
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if (do_write) {
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cmd = MemCmd::WriteReq;
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} else {
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cmd = MemCmd::ReadReq;
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}
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PacketPtr pkt = new Packet(req, cmd);
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pkt->allocate();
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if (port->sendTimingReq(pkt)) {
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DPRINTF(DirectedTest, "initiating request - successful\n");
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m_status = SeriesRequestGeneratorStatus_Request_Pending;
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return true;
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} else {
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// If the packet did not issue, must delete
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// Note: No need to delete the data, the packet destructor
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// will delete it
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delete pkt->req;
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delete pkt;
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DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n");
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return false;
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}
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}
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void
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SeriesRequestGenerator::performCallback(uint32_t proc, Addr address)
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{
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assert(m_active_node == proc);
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assert(m_address == address);
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assert(m_status == SeriesRequestGeneratorStatus_Request_Pending);
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m_status = SeriesRequestGeneratorStatus_Thinking;
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m_active_node++;
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if (m_active_node == m_num_cpus) {
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//
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// Cycle of requests completed, increment cycle completions and restart
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// at cpu zero
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//
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m_directed_tester->incrementCycleCompletions();
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m_address += m_addr_increment_size;
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m_active_node = 0;
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}
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}
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SeriesRequestGenerator *
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SeriesRequestGeneratorParams::create()
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{
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return new SeriesRequestGenerator(this);
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}
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