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arch-x86: Change insertBits in TLB translateFunctional

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x86 TLB::translateFunctional inserts one too many bits from the virtual
address leading to an incorrect physical address occasionally.

Change-Id: I2cc551c496f7ce729ea440ef01a680c0de257269
JIRA: https://gem5.atlassian.net/browse/GEM5-442
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27827
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2020-04-14 18:39:47 -07:00
parent 8a46b6b6b4
commit 20a4ed6f01
1 changed files with 1 additions and 1 deletions
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2
src/arch/x86/tlb.cc
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@@ -473,7 +473,7 @@ TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
Fault fault = walker->startFunctional(tc, addr, logBytes, mode);
if (fault != NoFault)
return fault;
paddr = insertBits(addr, logBytes, 0, vaddr);
paddr = insertBits(addr, logBytes - 1, 0, vaddr);
} else {
Process *process = tc->getProcessPtr();
const auto *pte = process->pTable->lookup(vaddr);