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x86: Move miscreg initialization to the ISA class.

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The initCPU function was setting a lot of values to zero or other
initial values, but that's something the ISA object can do as part of
its clear() method. This gets rid of a lot of code that was
individually zeroing registers, and also centralizes responsibility
for those registers in the ISA.

Change-Id: Iafcffd3f9329c39f77009b38b1696f91c36c117e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24185
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-01-09 00:53:15 -08:00
parent 7085b85614
commit 2012a0c651
2 changed files with 29 additions and 106 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
src/arch/x86/isa.cc
View File

@@ -108,8 +108,29 @@ ISA::clear()
// Blank everything. 0 might not be an appropriate value for some things,
// but it is for most.
memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
// If some state should be non-zero after a reset, set those values here.
regVal[MISCREG_CR0] = 0x0000000060000010ULL;
regVal[MISCREG_MTRRCAP] = 0x0508;
regVal[MISCREG_MCG_CAP] = 0x104;
regVal[MISCREG_PAT] = 0x0007040600070406ULL;
regVal[MISCREG_SYSCFG] = 0x20601;
regVal[MISCREG_TOP_MEM] = 0x4000000;
regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
regVal[MISCREG_DR7] = 1 << 10;
LocalApicBase lApicBase = 0;
lApicBase.base = 0xFEE00000 >> 12;
lApicBase.enable = 1;
// The "bsp" bit will be set when this register is read, since then we'll
// have a ThreadContext to check the contextId from.
regVal[MISCREG_APIC_BASE] = lApicBase;
}
ISA::ISA(Params *p)
@@ -148,6 +169,12 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
return insertBits(fsw, 13, 11, top);
}
if (miscReg == MISCREG_APIC_BASE) {
LocalApicBase base = regVal[MISCREG_APIC_BASE];
base.bsp = (tc->contextId() == 0);
return base;
}
return readMiscRegNoEffect(miscReg);
}

108
src/arch/x86/utility.cc
View File

@@ -71,7 +71,8 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
}
}
void initCPU(ThreadContext *tc, int cpuId)
void
initCPU(ThreadContext *tc, int cpuId)
{
// This function is essentially performing a reset. The actual INIT
// interrupt does a subset of this, so we'll piggyback on some of its
@@ -79,109 +80,11 @@ void initCPU(ThreadContext *tc, int cpuId)
InitInterrupt init(0);
init.invoke(tc);
PCState pc = tc->pcState();
pc.upc(0);
pc.nupc(1);
tc->pcState(pc);
// These next two loops zero internal microcode and implicit registers.
// They aren't specified by the ISA but are used internally by M5's
// implementation.
for (int index = 0; index < NumMicroIntRegs; index++) {
tc->setIntReg(INTREG_MICRO(index), 0);
}
for (int index = 0; index < NumImplicitIntRegs; index++) {
tc->setIntReg(INTREG_IMPLICIT(index), 0);
}
// Set integer register EAX to 0 to indicate that the optional BIST
// passed. No BIST actually runs, but software may still check this
// register for errors.
tc->setIntReg(INTREG_RAX, 0);
tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
tc->setMiscReg(MISCREG_CR8, 0);
// TODO initialize x87, 64 bit, and 128 bit media state
tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
for (int i = 0; i < 8; i++) {
tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
}
tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
tc->setMiscReg(MISCREG_DEF_TYPE, 0);
tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
tc->setMiscReg(MISCREG_MCG_STATUS, 0);
tc->setMiscReg(MISCREG_MCG_CTL, 0);
for (int i = 0; i < 5; i++) {
tc->setMiscReg(MISCREG_MC_CTL(i), 0);
tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
tc->setMiscReg(MISCREG_MC_MISC(i), 0);
}
tc->setMiscReg(MISCREG_TSC, 0);
tc->setMiscReg(MISCREG_TSC_AUX, 0);
for (int i = 0; i < 4; i++) {
tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
}
tc->setMiscReg(MISCREG_STAR, 0);
tc->setMiscReg(MISCREG_LSTAR, 0);
tc->setMiscReg(MISCREG_CSTAR, 0);
tc->setMiscReg(MISCREG_SF_MASK, 0);
tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
tc->setMiscReg(MISCREG_IORR_BASE0, 0);
tc->setMiscReg(MISCREG_IORR_BASE1, 0);
tc->setMiscReg(MISCREG_IORR_MASK0, 0);
tc->setMiscReg(MISCREG_IORR_MASK1, 0);
tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
// Invalidate the caches (this should already be done for us)
LocalApicBase lApicBase = 0;
lApicBase.base = 0xFEE00000 >> 12;
lApicBase.enable = 1;
lApicBase.bsp = (cpuId == 0);
tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
Interrupts * interrupts = dynamic_cast<Interrupts *>(
tc->getCpuPtr()->getInterruptController(0));
assert(interrupts);
@@ -189,13 +92,6 @@ void initCPU(ThreadContext *tc, int cpuId)
interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
// TODO Set the SMRAM base address (SMBASE) to 0x00030000
tc->setMiscReg(MISCREG_VM_CR, 0);
tc->setMiscReg(MISCREG_IGNNE, 0);
tc->setMiscReg(MISCREG_SMM_CTL, 0);
tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
}
void startupCPU(ThreadContext *tc, int cpuId)